XH-1 Research
Research repository for the XH-1, a custom 128-core RISC-V processor and the first processor in the XH-series.
This repository contains the research, experiments, architectural investigations, design decisions, prototypes, simulations, benchmarks, and technical notes produced during the development of XH-1.
The purpose of this repository is to capture the research and development process behind the processor, including ideas that may ultimately be implemented, ideas that are rejected, experimental results, and questions that remain unresolved.
This is intentionally separate from the main XH-1 documentation. The main documentation describes the processor's current architecture and implementation, while this repository records the research that leads to those decisions.
About XH-1
XH-1 is the first processor in the XH-series and is designed around a 128-core RISC-V architecture.
The project explores the design of a high-core-count processor, including:
- RISC-V ISA implementation
- CPU core architecture
- 128-core organization
- Multicore scalability
- Cache architecture
- Memory hierarchy
- Cache coherency
- Interconnect design
- Inter-core communication
- Synchronization
- Branch prediction
- Verification
- Simulation
- Performance
- FPGA implementation
- ASIC considerations
- Software and firmware
XH-1 is currently in the research and development phase. Architectural decisions may therefore change as new research and experimental results become available.
Purpose of This Repository
The primary purpose of this repository is to answer:
Why is XH-1 designed the way it is?
The main XH-1 documentation should describe what the processor currently does.
This repository describes:
- Why a particular architecture was considered
- What alternatives were investigated
- What experiments were performed
- What results were obtained
- Why particular designs were selected
- Why other designs were rejected
- What problems remain unsolved
- What ideas may be explored in the future
Research should be preserved even when an experiment does not produce the desired result.
Failed approaches are valuable because they prevent the same mistakes from being repeated and provide useful information for future XH-series processors.