90 lines
3.7 KiB
HTML
90 lines
3.7 KiB
HTML
<!DOCTYPE html>
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<html lang="en">
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<meta charset="UTF-8">
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<title>About - ReviveSparc</title>
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<body>
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<h1><a href="index.html">ReviveSparc</a></h1>
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<p class="subtitle">An open-source OpenSPARC ISA reimplementation</p>
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<div id="nav">
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<div class="inner">
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<ul>
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<li><a href="index.html">Home</a></li>
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<li><a href="about.html" class="active">About</a></li>
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<li><a href="download.html">Download</a></li>
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<li><a href="docs.html">Docs</a></li>
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<li><a href="news.html">News</a></li>
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<li><a href="roadmap.html">Roadmap</a></li>
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<li><a href="screenshots.html">Screenshots</a></li>
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<li><a href="community.html">Community</a></li>
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<li><a href="sponsors.html">Sponsors</a></li>
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<h2>About ReviveSparc</h2>
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<h3>History</h3>
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<p>The OpenSPARC project was launched by Sun Microsystems in 2006, releasing the UltraSPARC T1 and T2 processor designs as open-source hardware. The accompanying software — simulators, verification suites, and firmware — was released under the GPL. However, parts of the codebase originated from AT&T Unix source code, creating licensing uncertainty that prevented widespread adoption by the open-source community.</p>
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<p>ReviveSparc was started in early 2026 to address this. By rebuilding everything from the published ISA specification — without reference to the original source code — we provide a legally clean, fully open-source implementation.</p>
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<h3>Clean Room Process</h3>
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<p>We follow a strict clean-room methodology:</p>
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<ul>
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<li>Developers working on the implementation have <strong>no access</strong> to the original OpenSPARC source code.</li>
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<li>Only publicly available specification documents are used: the SPARC Architecture Manual v9, the UltraSPARC T1 Supplement, and the OpenSPARC specification.</li>
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<li>All new code is written from scratch, with no derived or translated code from the original project.</li>
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<li>The resulting code is licensed under the BSD 2-Clause License, permitting both open-source and proprietary use.</li>
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</ul>
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<h3>Project Goals</h3>
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<ul>
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<li><strong>Full SPARC V9 ISA compliance</strong> — user and privileged instructions, including VIS (Visual Instruction Set) extensions.</li>
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<li><strong>Multi-core simulation</strong> — support for chip-multithreading (CMT) as in the original T1/T2 designs.</li>
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<li><strong>Boot real operating systems</strong> — Linux, NetBSD, OpenBSD, and potentially Solaris.</li>
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<li><strong>Hardware implementation path</strong> — provide a Verilog RTL target for FPGA prototyping.</li>
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<li><strong>Educational resource</strong> — serve as a clean reference for students and researchers studying processor architecture.</li>
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</ul>
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<h3>Architecture Overview</h3>
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<p>ReviveSparc targets the UltraSPARC architecture profile:</p>
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<table>
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<tr><th>Feature</th><th>Description</th></tr>
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<tr><td>ISA</td><td>SPARC V9 (with VIS 1/2 extensions)</td></tr>
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<tr><td>Pipeline</td><td>6-stage, in-order, dual-issue</td></tr>
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<tr><td>Threading</td><td>4 threads per core (fine-grained CMT)</td></tr>
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<tr><td>Cores</td><td>1 to 8</td></tr>
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<tr><td>MMU</td><td>SPARC Reference MMU with TLB</td></tr>
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<tr><td>Cache</td><td>Split I/D L1, unified L2</td></tr>
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<tr><td>Interrupts</td><td>UltraSPARC-style interrupt controller</td></tr>
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</table>
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<h3>Repository Structure</h3>
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<pre>revivesparc/
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emu/ -- Functional instruction-set simulator
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rtl/ -- Verilog RTL for synthesis
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soft/ -- Firmware and boot ROM code
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tests/ -- ISA verification test suite
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tools/ -- Helper scripts and utilities
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docs/ -- Additional documentation</pre>
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</div>
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<div id="footer">
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<p>ReviveSparc is released under the BSD 2-Clause License.</p>
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</div>
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