116 lines
3.2 KiB
Markdown
116 lines
3.2 KiB
Markdown
# RTL Synthesis Guide
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This guide covers synthesizing the ReviveSparc Verilog RTL for FPGA deployment.
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## Overview
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The ReviveSparc RTL implements a 6-stage, in-order, dual-issue SPARC V9 pipeline with chip multi-threading. It is written in synthesizable Verilog and targets Xilinx and Intel FPGAs.
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## Pipeline Stages
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```
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Fetch --> Decode --> Execute --> Memory --> Writeback --> Commit
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v v v v v v
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ICache Decode ALU/MUL D-Cache RegFile TLB/MMU
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```
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## Prerequisites
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- **Verilator** 5.x (for simulation)
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- **Vivado** 2024.x or **Quartus** 23.x (for synthesis)
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- **Python** 3.10+ (for build scripts)
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- **FuseSoC** (optional, for IP management)
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## Building the RTL Simulation
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```bash
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make rtl
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```
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This compiles the RTL with Verilator and produces a simulation binary.
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### Running RTL Tests
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```bash
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make rtl-test
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```
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This runs the complete RTL test suite, including unit tests for each pipeline stage and integration tests for the full core.
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## FPGA Synthesis
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### Xilinx Vivado
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```bash
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cd rtl/syn/vivado
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vivado -mode batch -source synth.tcl
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```
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This generates a bitstream for the default target board.
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### Target Boards
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| Board | Speed | Resources Used | Status |
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|-------|-------|----------------|--------|
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| Xilinx VC707 (Virtex-7) | 50 MHz, 4 cores | 65% LUT, 48% BRAM | Verified |
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| Xilinx KC705 (Kintex-7) | 75 MHz, 2 cores | 55% LUT, 35% BRAM | Verified |
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| Xilinx Arty A7 (Artix-7) | 40 MHz, 1 core | 70% LUT, 60% BRAM | Verified |
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| Intel Arria 10 GX | 100 MHz, 4 cores | 60% ALM, 40% M20K | Verified |
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| Intel Cyclone V | 50 MHz, 2 cores | 72% ALM, 55% M20K | Beta |
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### Configuration
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RTL parameters are set in `rtl/config.vh`:
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```verilog
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`define NUM_CORES 4
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`define THREADS_PER_CORE 4
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`define L1I_SIZE 16384
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`define L1D_SIZE 16384
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`define L2_SIZE 1048576
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`define PIPELINE_STAGES 6
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```
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## Running on FPGA
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1. Program the FPGA with the generated bitstream
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2. Connect a USB-UART cable (default: 115200 baud, 8N1)
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3. Load a program via the boot ROM interface:
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```bash
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./tools/fpga-load.py /dev/ttyUSB0 kernel.bin
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```
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4. The core resets and begins execution. Output appears on the serial console.
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## Boot ROM
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The boot ROM loads a program from the UART interface into memory and starts execution at the entry point. The boot ROM firmware is in `soft/bootrom/` and is pre-synthesized into the bitstream.
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## Debug Interface
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The RTL includes a JTAG-like debug interface accessible via the emulator:
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```bash
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./sparc-emu --connect-fpga /dev/ttyUSB1
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```
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This connects the emulator's debugger to the FPGA-resident cores, allowing register inspection and breakpoint management.
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## Performance Results
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| Configuration | FPGA | Frequency | DMIPS |
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|---------------|------|-----------|-------|
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| 1 core, 4 threads | Artix-7 | 40 MHz | 45 |
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| 2 cores, 4 threads | Kintex-7 | 75 MHz | 168 |
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| 4 cores, 4 threads | Virtex-7 | 50 MHz | 320 |
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| 4 cores, 4 threads | Arria 10 | 100 MHz | 720 |
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## Contributing RTL Changes
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1. Write a Verilog testbench in `rtl/tb/`
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2. Verify with Verilator: `make rtl-test`
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3. Ensure lint passes: `make rtl-lint`
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4. Submit a pull request with simulation results
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