138 lines
4.2 KiB
Markdown
138 lines
4.2 KiB
Markdown
# SPARC V9 ISA Reference
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Reference documentation for the SPARC V9 instruction set as implemented in ReviveSparc.
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## Overview
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The SPARC V9 architecture is a 64-bit RISC ISA developed by Sun Microsystems and standardized by SPARC International. ReviveSparc implements the full SPARC V9 specification, including the VIS (Visual Instruction Set) extensions.
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### Key Features
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- 64-bit integer and floating-point registers
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- 32 general-purpose registers (register windowed)
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- 32 floating-point registers (quad-precision capable)
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- Delayed branching with annulment
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- Register windowing with 8 global + up to 32 windowed registers
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- Precise exceptions and multiple trap levels
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## Instruction Set Categories
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### Integer Instructions
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```
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ADD Add ADDcc Add and modify CC
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AND And ANDcc And and modify CC
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OR Or ORcc Or and modify CC
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XOR Exclusive Or XORcc Exclusive Or and modify CC
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SUB Subtract SUBcc Subtract and modify CC
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MULX Multiply Extended UDIVX Unsigned Divide Extended
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SDIVX Signed Divide Extended
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SLL Shift Left Logical SRL Shift Right Logical
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SRA Shift Right Arithmetic
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```
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### Load/Store Instructions
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```
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LDUB Load Unsigned Byte
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LDSB Load Signed Byte
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LDUH Load Unsigned Halfword
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LDSH Load Signed Halfword
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LDW Load Word
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LDX Load Doubleword
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STB Store Byte
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STH Store Halfword
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STW Store Word
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STX Store Doubleword
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LDF Load Floating-point
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LDDF Load Double Floating-point
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STF Store Floating-point
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STDF Store Double Floating-point
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```
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### Branch Instructions
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```
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Bcc Branch on Condition
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BPcc Branch on Condition (Predicted)
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BPr Branch on Register
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CALL Call and Link
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RETT Return from Trap
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JMPL Jump and Link
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RETURN Return from Subroutine
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```
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### Floating-Point Instructions
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```
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FADDs FP Add (single)
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FADDd FP Add (double)
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FSUBs FP Subtract (single)
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FSUBd FP Subtract (double)
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FMULs FP Multiply (single)
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FMULd FP Multiply (double)
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FDIVs FP Divide (single)
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FDIVd FP Divide (double)
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FSQRTs FP Square Root (single)
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FSQRTd FP Square Root (double)
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F CMPs FP Compare (single)
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F CMPd FP Compare (double)
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```
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### VIS Instructions
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```
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FPACK16 Pack 16-bit
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FPACK32 Pack 32-bit
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FALIGNDATA Align Data
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FEXPAND Expand
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FMUL8x16 Multiply 8-bit by 16-bit
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FMUL8x16AU Multiply 8-bit by 16-bit (unsigned)
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FMUL8x16AL Multiply 8-bit by 16-bit (unsigned)
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FMUL8SUx16 Multiply 8-bit Signed by 16-bit Unsigned
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FMUL8ULx16 Multiply 8-bit Unsigned by 16-bit Unsigned
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FMULD8SUx16 Multiply Double 8-bit Signed by 16-bit Unsigned
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FMULD8ULx16 Multiply Double 8-bit Unsigned by 16-bit Unsigned
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```
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## Register Windows
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SPARC V9 uses register windows to optimize function call performance:
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- **8 global registers** (%g0 through %g7, where %g0 is always zero)
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- **Up to 32 register windows**, each containing 16 registers
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- Each window provides: 8 incoming (%i0-%i7), 8 local (%l0-%l7), 8 outgoing (%o0-%o7) — with overlap between adjacent windows
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- The number of windows is implementation-dependent
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## Privileged Registers
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| Register | Description |
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|----------|-------------|
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| TPC | Trap PC (1-4) |
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| TNPC | Trap Next PC (1-4) |
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| TSTATE | Trap State (1-4) |
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| TT | Trap Type (1-4) |
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| TBA | Trap Base Address |
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| PSTATE | Processor State |
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| TL | Trap Level |
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| PIL | Processor Interrupt Level |
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| CWP | Current Window Pointer |
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| CANSAVE | Cleanable Windows |
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| CANRESTORE | Restorable Windows |
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## Trap Types
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| TT Value | Trap Name | Description |
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|----------|-----------|-------------|
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| 0x01 | instruction_access_exception | Memory access fault |
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| 0x03 | instruction_access_error | Hardware error |
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| 0x04 | illegal_instruction | Unimplemented instruction |
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| 0x05 | privileged_operation | Trap in user mode |
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| 0x06 | fp_disabled | FPU not enabled |
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| 0x08 | clean_window | Register window spill needed |
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| 0x09 | division_by_zero | Integer divide by zero |
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| 0x20-0x2f | interrupt_vector | External interrupts |
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| 0x60-0x7f | software_trap | `ta` instruction traps |
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| 0x80 | data_access_exception | Data memory access fault |
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| 0x82 | data_access_error | Data memory hardware error |
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