135 lines
3.2 KiB
Markdown
135 lines
3.2 KiB
Markdown
# Memory Model
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ReviveSparc implements the SPARC V9 memory architecture, including the cache hierarchy, MMU, and memory ordering models.
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## Cache Hierarchy
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```
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CLIENT (Core)
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+-- L1 I-Cache (16 KB, 4-way, 32-byte line)
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+-- L1 D-Cache (16 KB, 4-way, 32-byte line)
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+-- L2 Cache (shared, 512 KB - 4 MB, 8-way)
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+-- Main Memory (DDR4, configurable)
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```
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### L1 Caches
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- **Capacity**: 16 KB each for instructions and data
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- **Associativity**: 4-way set associative
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- **Line size**: 32 bytes
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- **Latency**: 2 cycles (hit), 1 cycle (tag check)
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- **Policy**: Write-back (D-cache), read-only (I-cache)
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- **Coherency**: MOESI protocol between cores
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### L2 Cache
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- **Capacity**: Configurable (512 KB to 4 MB)
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- **Associativity**: 8-way set associative
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- **Line size**: 64 bytes
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- **Latency**: 12 cycles (hit)
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- **Policy**: Write-back, write-allocate
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- **Coherency**: Inclusive of L1 (snoop filter)
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## MMU (Memory Management Unit)
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The SPARC Reference MMU provides virtual-to-physical address translation.
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### Address Spaces
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| Mode | Virtual Address Width | Physical Address Width |
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|------|----------------------|----------------------|
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| 32-bit (V8 compat) | 32 bits | 40 bits |
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| 64-bit (V9) | 44 bits | 44 bits |
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### TLB Structure
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```
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ITLB (64 entries)
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Fully associative
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Supports 8 KB, 64 KB, 256 KB, 4 MB pages
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DTLB (64 entries)
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Fully associative
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Supports same page sizes as ITLB
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```
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### Translation Process
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```
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Virtual Address (44 bits)
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+-- VPN[0:2] --> TLB Lookup (parallel)
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| +-- Hit? --> PPN + Offset --> Physical Address
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| +-- Miss --> TLB Miss Trap (TLB miss handler)
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+-- Offset --> Direct to physical address
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```
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### TSB (Translation Storage Buffer)
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The TSB is a software-managed cache of page table entries. On a TLB miss, the trap handler searches the TSB before walking the full page table.
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## Memory Ordering
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ReviveSparc supports three memory models:
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### Total Store Order (TSO)
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The default SPARC V9 model:
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- Stores appear in program order to all observers
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- Loads may pass stores (store buffer forwarding)
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- Atomic operations provide full ordering
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### Partial Store Order (PSO)
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Relaxed store ordering:
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- Stores to different locations may be reordered
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- Stores to the same location appear in order
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- MEMBAR is required for ordering constraints
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### Relaxed Memory Order (RMO)
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Maximum relaxation:
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- Loads and stores may be reordered freely
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- All ordering is explicit via MEMBAR instructions
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- Highest performance on multi-core configurations
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## Atomic Operations
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| Instruction | Description |
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|-------------|-------------|
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| `CAS` | Compare and Swap (32-bit) |
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| `CASX` | Compare and Swap (64-bit) |
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| `SWAP` | Atomic swap |
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| `LDSTUB` | Atomic load-and-store-byte |
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| `CASA` | Compare and Swap (alternate space) |
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| `CASXA` | Compare and Swap (alternate space, 64-bit) |
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## Configuration
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Memory parameters can be configured at startup:
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```bash
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./sparc-emu -l1i 16k -l1d 16k -l2 1m -mem tso kernel.bin
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```
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Or via the C API:
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```c
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sparc_mem_config_t mem = {
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.l1i_size = 16 * 1024,
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.l1d_size = 16 * 1024,
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.l2_size = 1 * 1024 * 1024,
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.memory_model = MEM_TSO,
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.num_cores = 4
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};
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sparc_t *cpu = sparc_new_with_config(&mem);
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```
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