Updates

2026-08-26 18:42:44 +02:00
parent 03616cd150
commit ac7a7ff35d
8 changed files with 49 additions and 43 deletions
@@ -112,4 +112,4 @@ This connects the emulator's debugger to the FPGA-resident cores, allowing regis
 1. Write a Verilog testbench in `rtl/tb/`
 2. Verify with Verilator: `make rtl-test`
 3. Ensure lint passes: `make rtl-lint`
-4. Submit a pull request with simulation results
+4. Submit a pull request on the [Git instance](https://git.revivesparc.com/Revivesparc/revivesparc) with simulation results