A: Initial

README.MD

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+# XH-1 Research
+
+Research repository for the **XH-1**, a custom **128-core RISC-V processor** and the first processor in the XH-series.
+
+This repository contains the research, experiments, architectural investigations, design decisions, prototypes, simulations, benchmarks, and technical notes produced during the development of XH-1.
+
+The purpose of this repository is to capture the **research and development process behind the processor**, including ideas that may ultimately be implemented, ideas that are rejected, experimental results, and questions that remain unresolved.
+
+This is intentionally separate from the main XH-1 documentation. The main documentation describes the processor's current architecture and implementation, while this repository records the research that leads to those decisions.
+
+---
+
+## About XH-1
+
+**XH-1** is the first processor in the XH-series and is designed around a **128-core RISC-V architecture**.
+
+The project explores the design of a high-core-count processor, including:
+
+- RISC-V ISA implementation
+- CPU core architecture
+- 128-core organization
+- Multicore scalability
+- Cache architecture
+- Memory hierarchy
+- Cache coherency
+- Interconnect design
+- Inter-core communication
+- Synchronization
+- Branch prediction
+- Verification
+- Simulation
+- Performance
+- FPGA implementation
+- ASIC considerations
+- Software and firmware
+
+XH-1 is currently in the research and development phase. Architectural decisions may therefore change as new research and experimental results become available.
+
+---
+
+# Purpose of This Repository
+
+The primary purpose of this repository is to answer:
+
+> **Why is XH-1 designed the way it is?**
+
+The main XH-1 documentation should describe what the processor currently does.
+
+This repository describes:
+
+- Why a particular architecture was considered
+- What alternatives were investigated
+- What experiments were performed
+- What results were obtained
+- Why particular designs were selected
+- Why other designs were rejected
+- What problems remain unsolved
+- What ideas may be explored in the future
+
+Research should be preserved even when an experiment does not produce the desired result.
+
+Failed approaches are valuable because they prevent the same mistakes from being repeated and provide useful information for future XH-series processors.

research/00-overview/overview.md

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+# overview
+
+SOON

research/00-overview/questions.md

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+# questions
+
+SOON

research/00-overview/research-goals.md

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+# research goals
+
+SOON

research/00-overview/status.md

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+# status
+
+SOON

research/00-overview/terminology.md

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+# terminology
+
+SOON

research/01-architecture/alternatives.md

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+# alternatives
+
+SOON

research/01-architecture/architecture-overview.md

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+# architecture overview
+
+SOON

research/01-architecture/block-diagrams.md

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+# block diagrams
+
+SOON

research/01-architecture/constraints.md

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+# constraints
+
+SOON

research/01-architecture/design-space.md

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+# design space
+
+SOON

research/01-architecture/microarchitecture.md

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+# microarchitecture
+
+SOON

research/01-architecture/requirements.md

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+# requirements
+
+SOON

research/02-riscv/base-isa.md

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+# base isa
+
+SOON

research/02-riscv/csr.md

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+# csr
+
+SOON

research/02-riscv/custom-extensions.md

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+# custom extensions
+
+SOON

research/02-riscv/exceptions.md

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+# exceptions
+
+SOON

research/02-riscv/extensions.md

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+# extensions
+
+SOON

research/02-riscv/interrupts.md

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+# interrupts
+
+SOON

research/02-riscv/isa-overview.md

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+# isa overview
+
+SOON

research/02-riscv/privilege-model.md

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+# privilege model
+
+SOON

research/03-core-design/alu.md

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+# alu
+
+SOON

research/03-core-design/branch-unit.md

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+# branch unit
+
+SOON

research/03-core-design/control-unit.md

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+# control unit
+
+SOON

research/03-core-design/core-overview.md

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+# core overview
+
+SOON

research/03-core-design/datapath.md

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+# datapath
+
+SOON

research/03-core-design/decoder.md

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+# decoder
+
+SOON

research/03-core-design/load-store-unit.md

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+# load store unit
+
+SOON

research/03-core-design/mul-div-unit.md

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+# mul div unit
+
+SOON

research/03-core-design/pipeline.md

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+# pipeline
+
+SOON

research/03-core-design/register-file.md

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+# register file
+
+SOON

research/04-128-core/clusters.md

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+# clusters
+
+SOON

research/04-128-core/core-communication.md

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+# core communication
+
+SOON

research/04-128-core/core-numbering.md

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+# core numbering
+
+SOON

research/04-128-core/core-organization.md

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+# core organization
+
+SOON

research/04-128-core/inter-core-interrupts.md

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+# inter core interrupts
+
+SOON

research/04-128-core/overview.md

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+# overview
+
+SOON

research/04-128-core/scalability.md

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+# scalability
+
+SOON

research/04-128-core/synchronization.md

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+# synchronization
+
+SOON

research/04-128-core/topology.md

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+# topology
+
+SOON

research/05-memory/address-space.md

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+# address space
+
+SOON

research/05-memory/atomics.md

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+# atomics
+
+SOON

research/05-memory/cache-coherency.md

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+# cache coherency
+
+SOON

research/05-memory/cache-research.md

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+# cache research
+
+SOON

research/05-memory/memory-architecture.md

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+# memory architecture
+
+SOON

research/05-memory/memory-bandwidth.md

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+# memory bandwidth
+
+SOON

research/05-memory/memory-hierarchy.md

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+# memory hierarchy
+
+SOON

research/05-memory/memory-map.md

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+# memory map
+
+SOON

research/05-memory/memory-ordering.md

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+# memory ordering
+
+SOON

research/06-interconnect/arbitration.md

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+# arbitration
+
+SOON

research/06-interconnect/bandwidth.md

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+# bandwidth
+
+SOON

research/06-interconnect/flow-control.md

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+# flow control
+
+SOON

research/06-interconnect/latency.md

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+# latency
+
+SOON

research/06-interconnect/overview.md

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+# overview
+
+SOON

research/06-interconnect/protocol.md

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+# protocol
+
+SOON

research/06-interconnect/routing.md

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+# routing
+
+SOON

research/06-interconnect/scalability.md

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+# scalability
+
+SOON

research/06-interconnect/topology.md

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+# topology
+
+SOON

research/07-branch-prediction/bht.md

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+# bht
+
+SOON

research/07-branch-prediction/branch-history.md

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+# branch history
+
+SOON

research/07-branch-prediction/btb.md

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+# btb
+
+SOON

research/07-branch-prediction/experiments.md

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+# experiments
+
+SOON

research/07-branch-prediction/overview.md

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+# overview
+
+SOON

research/07-branch-prediction/prediction-algorithms.md

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+# prediction algorithms
+
+SOON

research/07-branch-prediction/ras.md

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+# ras
+
+SOON

research/08-cache/cache-benchmarks.md

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+# cache benchmarks
+
+SOON

research/08-cache/coherency.md

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+# coherency
+
+SOON

research/08-cache/l1.md

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+# l1
+
+SOON

research/08-cache/l2.md

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+# l2
+
+SOON

research/08-cache/l3.md

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+# l3
+
+SOON

research/08-cache/overview.md

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+# overview
+
+SOON

research/08-cache/prefetching.md

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+# prefetching
+
+SOON

research/08-cache/replacement-policy.md

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+# replacement policy
+
+SOON

research/09-multicore/atomics.md

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+# atomics
+
+SOON

research/09-multicore/barriers.md

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+# barriers
+
+SOON

research/09-multicore/contention.md

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+# contention
+
+SOON

research/09-multicore/load-balancing.md

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+# load balancing
+
+SOON

research/09-multicore/locks.md

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+# locks
+
+SOON

research/09-multicore/parallelism.md

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+# parallelism
+
+SOON

research/09-multicore/scaling.md

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+# scaling
+
+SOON

research/09-multicore/scheduling.md

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+# scheduling
+
+SOON

research/10-verification/core-verification.md

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+# core verification
+
+SOON

research/10-verification/fault-injection.md

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+# fault injection
+
+SOON

research/10-verification/formal-verification.md

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+# formal verification
+
+SOON

research/10-verification/isa-compliance.md

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+# isa compliance
+
+SOON

research/10-verification/multicore-verification.md

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+# multicore verification
+
+SOON

research/10-verification/regression.md

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+# regression
+
+SOON

research/10-verification/strategy.md

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+# strategy
+
+SOON

research/10-verification/unit-verification.md

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+# unit verification
+
+SOON

research/11-simulation/behavioral-model.md

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+# behavioral model
+
+SOON

research/11-simulation/cycle-accurate-model.md

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+# cycle accurate model
+
+SOON

research/11-simulation/rtl-simulation.md

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+# rtl simulation
+
+SOON

research/11-simulation/simulation-overview.md

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+# simulation overview
+
+SOON

research/11-simulation/simulators.md

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+# simulators
+
+SOON

research/11-simulation/testbenches.md

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+# testbenches
+
+SOON

research/11-simulation/waveforms.md

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+# waveforms
+
+SOON

research/12-performance/benchmarks.md

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+# benchmarks
+
+SOON

research/12-performance/bottlenecks.md

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+# bottlenecks
+
+SOON

research/12-performance/interconnect-performance.md

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+# interconnect performance
+
+SOON

research/12-performance/memory-performance.md

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+# memory performance
+
+SOON