mirror of
https://github.com/allexanderbergmns/xh1-research.git
synced 2026-08-26 16:47:01 +00:00
PASS: Completed Review | research/05-memory/memory-bandwidth.md
This commit is contained in:
allexanderbergmns
@@ -67,6 +67,7 @@ OLLAMA_CONTEXT="${OLLAMA_CONTEXT:-16384}"
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# ------------------------------------------------------------
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# ------------------------------------------------------------
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OPENROUTER_URL="${OPENROUTER_URL:-https://openrouter.ai/api/v1}"
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OPENROUTER_URL="${OPENROUTER_URL:-https://openrouter.ai/api/v1}"
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QWEN_URL="${QWEN_URL:-https://dashscope-intl.aliyuncs.com/compatible-mode/v1}"
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OLLAMA_URL="${OLLAMA_URL:-http://127.0.0.1:11434/v1}"
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OLLAMA_URL="${OLLAMA_URL:-http://127.0.0.1:11434/v1}"
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OPENROUTER_KEY_ENV="${OPENROUTER_KEY_ENV:-OPENROUTER_API_KEY}"
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OPENROUTER_KEY_ENV="${OPENROUTER_KEY_ENV:-OPENROUTER_API_KEY}"
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@@ -237,6 +238,10 @@ provider_url() {
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printf '%s' "$OLLAMA_URL"
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printf '%s' "$OLLAMA_URL"
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;;
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;;
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qwen)
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printf '%s' "$QWEN_URL"
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;;
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*)
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*)
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local variable="PROVIDER_${provider}_URL"
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local variable="PROVIDER_${provider}_URL"
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local value="${!variable:-}"
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local value="${!variable:-}"
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@@ -265,6 +270,11 @@ provider_key() {
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printf '%s' "${!env:-}"
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printf '%s' "${!env:-}"
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;;
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;;
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qwen)
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local env="${QWEN_KEY_ENV:-QWEN_API_KEY}"
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printf '%s' "${!env:-}"
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;;
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*)
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*)
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local env_var="PROVIDER_${provider}_KEY_ENV"
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local env_var="PROVIDER_${provider}_KEY_ENV"
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local env="${!env_var:-}"
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local env="${!env_var:-}"
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@@ -1550,6 +1560,11 @@ providers() {
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"$OLLAMA_URL" \
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"$OLLAMA_URL" \
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"$REVIEW_MODEL"
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"$REVIEW_MODEL"
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printf '%-15s %-45s %s\n' \
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"qwen" \
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"$QWEN_URL" \
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"$RESEARCH_MODEL"
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echo
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echo
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echo "Research:"
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echo "Research:"
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echo " $RESEARCH_PROVIDER / $RESEARCH_MODEL"
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echo " $RESEARCH_PROVIDER / $RESEARCH_MODEL"
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@@ -474,3 +474,219 @@
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[2026-08-26T13:02:54Z] Response received: 2234 bytes
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[2026-08-26T13:02:54Z] Response received: 2234 bytes
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[2026-08-26T13:02:54Z] Research passed review.
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[2026-08-26T13:02:54Z] Research passed review.
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[2026-08-26T13:02:54Z] Accepted research document: research/05-memory/memory-architecture.md
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[2026-08-26T13:02:54Z] Accepted research document: research/05-memory/memory-architecture.md
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[2026-08-26T13:19:26Z] Started run: 20260826T131926Z
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[2026-08-26T13:19:26Z] ==================================================
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[2026-08-26T13:19:26Z] Researching: research/05-memory/memory-bandwidth.md
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[2026-08-26T13:19:26Z] ==================================================
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[2026-08-26T13:19:26Z] Research round 1/3
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[2026-08-26T13:19:26Z] Running researcher.
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[2026-08-26T13:19:27Z] API: provider=openrouter model=minimax/minimax-m3:free attempt=1
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[2026-08-26T13:20:19Z] Response received: 20125 bytes
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[2026-08-26T13:20:19Z] Running reviewer.
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[2026-08-26T13:20:19Z] API: provider=qwen model=qwen3.7-plus attempt=1
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[2026-08-26T13:20:28Z] API: provider=qwen model=qwen3.7-plus attempt=3
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[2026-08-26T13:20:28Z] WARNING: Network/API connection failure.
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[2026-08-26T13:21:34Z] Started run: 20260826T132134Z
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[2026-08-26T13:21:34Z] ==================================================
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[2026-08-26T13:21:34Z] Researching: research/05-memory/memory-bandwidth.md
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[2026-08-26T13:21:34Z] ==================================================
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[2026-08-26T13:21:34Z] Research round 1/3
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[2026-08-26T13:21:34Z] Running researcher.
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[2026-08-26T13:21:37Z] API: provider=openrouter model=minimax/minimax-m3:free attempt=2
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[2026-08-26T13:21:38Z] WARNING: Client/API error from openrouter.
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[2026-08-26T13:21:44Z] API: provider=openrouter model=minimax/minimax-m3:free attempt=3
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[2026-08-26T13:21:44Z] API HTTP status: 401
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[2026-08-26T13:21:44Z] WARNING: Client/API error from openrouter.
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[2026-08-26T13:21:44Z] WARNING: API request exhausted all retries.
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[2026-08-26T13:21:44Z] WARNING: Research API failed.
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[2026-08-26T13:21:44Z] WARNING: Topic will NOT be marked as failed.
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[2026-08-26T13:21:46Z] Started run: 20260826T132146Z
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[2026-08-26T13:21:46Z] ==================================================
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[2026-08-26T13:21:46Z] Researching: research/05-memory/memory-bandwidth.md
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[2026-08-26T13:21:46Z] ==================================================
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[2026-08-26T13:21:46Z] Research round 1/3
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[2026-08-26T13:21:46Z] Running researcher.
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[2026-08-26T13:21:46Z] API: provider=openrouter model=minimax/minimax-m3:free attempt=1
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[2026-08-26T13:21:47Z] WARNING: Client/API error from openrouter.
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[2026-08-26T13:23:02Z] Started run: 20260826T132302Z
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[2026-08-26T13:23:02Z] ==================================================
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[2026-08-26T13:23:02Z] Researching: research/05-memory/memory-bandwidth.md
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[2026-08-26T13:23:02Z] ==================================================
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[2026-08-26T13:23:02Z] Research round 1/3
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[2026-08-26T13:23:02Z] Running researcher.
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[2026-08-26T13:23:05Z] WARNING: Network/API connection failure.
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[2026-08-26T13:23:29Z] Started run: 20260826T132329Z
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[2026-08-26T13:23:29Z] ==================================================
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[2026-08-26T13:23:29Z] Researching: research/05-memory/memory-bandwidth.md
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[2026-08-26T13:23:29Z] ==================================================
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[2026-08-26T13:23:29Z] Research round 1/3
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[2026-08-26T13:23:29Z] Running researcher.
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[2026-08-26T13:23:29Z] API: provider=qwen model=qwen3.8-max attempt=1
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[2026-08-26T13:25:56Z] Started run: 20260826T132556Z
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[2026-08-26T13:25:56Z] ==================================================
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[2026-08-26T13:25:56Z] Researching: research/05-memory/memory-bandwidth.md
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[2026-08-26T13:25:56Z] ==================================================
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[2026-08-26T13:25:56Z] Research round 1/3
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[2026-08-26T13:25:56Z] Running researcher.
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[2026-08-26T13:25:56Z] API: provider=qwen model=qwen3.8-max attempt=1
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[2026-08-26T13:25:56Z] API HTTP status: 000
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[2026-08-26T13:25:56Z] WARNING: Network/API connection failure.
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[2026-08-26T13:26:07Z] Started run: 20260826T132607Z
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[2026-08-26T13:26:07Z] ==================================================
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[2026-08-26T13:26:07Z] Researching: research/05-memory/memory-bandwidth.md
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[2026-08-26T13:26:07Z] ==================================================
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[2026-08-26T13:26:07Z] Research round 1/3
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[2026-08-26T13:26:07Z] Running researcher.
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[2026-08-26T13:26:07Z] API: provider=qwen model=qwen3.8-max attempt=1
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[2026-08-26T13:26:07Z] API HTTP status: 000
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[2026-08-26T13:26:07Z] WARNING: Network/API connection failure.
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[2026-08-26T13:26:13Z] Started run: 20260826T132613Z
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[2026-08-26T13:26:13Z] ==================================================
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[2026-08-26T13:26:13Z] Researching: research/05-memory/memory-bandwidth.md
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[2026-08-26T13:26:13Z] ==================================================
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[2026-08-26T13:26:13Z] Research round 1/3
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[2026-08-26T13:26:13Z] Running researcher.
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[2026-08-26T13:26:50Z] Started run: 20260826T132650Z
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[2026-08-26T13:26:50Z] ==================================================
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[2026-08-26T13:26:50Z] Researching: research/05-memory/memory-bandwidth.md
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[2026-08-26T13:26:50Z] ==================================================
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[2026-08-26T13:26:50Z] Research round 1/3
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[2026-08-26T13:26:50Z] WARNING: Network/API connection failure.
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[2026-08-26T13:27:40Z] Started run: 20260826T132740Z
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||||||
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[2026-08-26T13:27:40Z] ==================================================
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[2026-08-26T13:27:40Z] Researching: research/05-memory/memory-bandwidth.md
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[2026-08-26T13:27:40Z] ==================================================
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[2026-08-26T13:27:57Z] Started run: 20260826T132757Z
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||||||
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[2026-08-26T13:27:57Z] ==================================================
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[2026-08-26T13:27:57Z] Researching: research/05-memory/memory-bandwidth.md
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[2026-08-26T13:27:57Z] ==================================================
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[2026-08-26T13:27:57Z] WARNING: Network/API connection failure.
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[2026-08-26T13:28:46Z] Started run: 20260826T132846Z
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||||||
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[2026-08-26T13:28:46Z] ==================================================
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[2026-08-26T13:28:46Z] Researching: research/05-memory/memory-bandwidth.md
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[2026-08-26T13:28:46Z] ==================================================
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[2026-08-26T13:28:46Z] Research round 1/3
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[2026-08-26T13:28:46Z] Running researcher.
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[2026-08-26T13:29:00Z] WARNING: Client/API error from qwen.
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[2026-08-26T13:29:03Z] API: provider=qwen model=qwen3.8-max attempt=2
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[2026-08-26T13:29:14Z] Started run: 20260826T132914Z
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[2026-08-26T13:29:14Z] ==================================================
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[2026-08-26T13:29:14Z] Researching: research/05-memory/memory-bandwidth.md
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[2026-08-26T13:29:14Z] ==================================================
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[2026-08-26T13:29:59Z] Started run: 20260826T132959Z
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||||||
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[2026-08-26T13:29:59Z] ==================================================
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[2026-08-26T13:29:59Z] Researching: research/05-memory/memory-bandwidth.md
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[2026-08-26T13:29:59Z] ==================================================
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[2026-08-26T13:30:40Z] Started run: 20260826T133040Z
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[2026-08-26T13:30:59Z] Started run: 20260826T133059Z
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[2026-08-26T13:31:32Z] Started run: 20260826T133132Z
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[2026-08-26T13:31:32Z] ==================================================
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[2026-08-26T13:31:32Z] Researching: research/05-memory/memory-bandwidth.md
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[2026-08-26T13:31:32Z] ==================================================
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[2026-08-26T13:31:33Z] WARNING: Client/API error from qwen.
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[2026-08-26T13:31:55Z] Started run: 20260826T133155Z
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[2026-08-26T13:31:55Z] ==================================================
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[2026-08-26T13:31:55Z] Researching: research/05-memory/memory-bandwidth.md
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[2026-08-26T13:31:55Z] ==================================================
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[2026-08-26T13:39:15Z] Started run: 20260826T133915Z
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||||||
|
[2026-08-26T13:39:15Z] ==================================================
|
||||||
|
[2026-08-26T13:39:15Z] Researching: research/05-memory/memory-bandwidth.md
|
||||||
|
[2026-08-26T13:39:15Z] ==================================================
|
||||||
|
[2026-08-26T13:39:15Z] Research round 1/3
|
||||||
|
[2026-08-26T13:39:15Z] Running researcher.
|
||||||
|
[2026-08-26T13:39:15Z] API: provider=qwen model=qwen3.8-max attempt=1
|
||||||
|
[2026-08-26T13:41:06Z] Started run: 20260826T134106Z
|
||||||
|
[2026-08-26T13:41:06Z] ==================================================
|
||||||
|
[2026-08-26T13:41:06Z] Researching: research/05-memory/memory-bandwidth.md
|
||||||
|
[2026-08-26T13:41:06Z] ==================================================
|
||||||
|
[2026-08-26T13:41:06Z] Research round 1/3
|
||||||
|
[2026-08-26T13:41:06Z] Running researcher.
|
||||||
|
[2026-08-26T13:41:06Z] API: provider=qwen model=qwen3.7-plus attempt=1
|
||||||
|
[2026-08-26T13:43:49Z] Started run: 20260826T134349Z
|
||||||
|
[2026-08-26T13:43:49Z] ==================================================
|
||||||
|
[2026-08-26T13:43:49Z] Researching: research/05-memory/memory-bandwidth.md
|
||||||
|
[2026-08-26T13:43:49Z] ==================================================
|
||||||
|
[2026-08-26T13:43:49Z] Research round 1/3
|
||||||
|
[2026-08-26T13:43:49Z] Running researcher.
|
||||||
|
[2026-08-26T13:43:49Z] API: provider=qwen model=qwen3.7-plus attempt=1
|
||||||
|
[2026-08-26T13:45:21Z] Response received: 11713 bytes
|
||||||
|
[2026-08-26T13:45:21Z] Running reviewer.
|
||||||
|
[2026-08-26T13:45:21Z] API: provider=qwen model=deepseek-v4-pro attempt=1
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||||||
|
[2026-08-26T13:47:18Z] Response received: 1142 bytes
|
||||||
|
[2026-08-26T13:47:18Z] Research passed review.
|
||||||
|
[2026-08-26T13:47:18Z] Accepted research document: research/05-memory/memory-bandwidth.md
|
||||||
|
[2026-08-26T13:47:58Z] Started run: 20260826T134758Z
|
||||||
|
[2026-08-26T13:47:58Z] ==================================================
|
||||||
|
[2026-08-26T13:47:58Z] Researching: research/05-memory/atomics.md
|
||||||
|
[2026-08-26T13:47:58Z] ==================================================
|
||||||
|
[2026-08-26T13:47:58Z] Research round 1/3
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||||||
|
[2026-08-26T13:47:58Z] Running researcher.
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[2026-08-26T13:47:58Z] API: provider=qwen model=qwen3.7-plus attempt=1
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2026-08-26T13:20:19Z research/05-memory/memory-bandwidth.md 1 research success
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|
# Memory Bandwidth
|
||||||
|
|
||||||
|
## Scope
|
||||||
|
|
||||||
|
This document investigates memory bandwidth requirements, limits, and
|
||||||
|
implementation strategies for the XH-1 processor, a proposed 128-core
|
||||||
|
RISC-V design. The discussion covers off-chip DRAM bandwidth,
|
||||||
|
on-chip interconnect bandwidth, cache hierarchy bandwidth, and the
|
||||||
|
interactions between bandwidth, coherence traffic, and the memory
|
||||||
|
system.
|
||||||
|
|
||||||
|
This document is part of the XH-1 research series (area 05-memory).
|
||||||
|
Statements about XH-1 implementation are proposals unless explicitly
|
||||||
|
marked as decided.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 1. Problem Statement
|
||||||
|
|
||||||
|
A 128-core processor generates substantially more memory traffic than
|
||||||
|
single-core or small-count-core designs. Even if each core issues a
|
||||||
|
modest number of outstanding memory requests, the aggregate demand can
|
||||||
|
quickly exceed the bandwidth available from a realistic DRAM subsystem.
|
||||||
|
|
||||||
|
The XH-1 design must therefore answer several related questions:
|
||||||
|
|
||||||
|
- How much DRAM bandwidth is physically available on the target package?
|
||||||
|
- How much of that bandwidth is consumed by coherence traffic?
|
||||||
|
- How much remains for useful application work?
|
||||||
|
- How is that remaining bandwidth shared between cores without
|
||||||
|
starvation or severe unfairness?
|
||||||
|
- Where do bandwidth bottlenecks arise in the on-chip interconnect,
|
||||||
|
cache hierarchy, and memory controllers?
|
||||||
|
|
||||||
|
The remainder of this document analyses each of these questions.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 2. Background
|
||||||
|
|
||||||
|
### 2.1 DRAM Bandwidth Fundamentals
|
||||||
|
|
||||||
|
Modern DDR systems provide bandwidth through wide channels and high
|
||||||
|
transfer rates:
|
||||||
|
|
||||||
|
- DDR5 devices use 32-bit sub-channels per module rank, with
|
||||||
|
transfer rates up to 8400 MT/s in JEDEC-published modules.
|
||||||
|
- A single DDR5 channel (64 bits) at 6400 MT/s delivers approximately
|
||||||
|
51.2 GB/s peak; a dual-channel configuration roughly doubles this.
|
||||||
|
- HBM3 stacks deliver substantially higher bandwidth per package
|
||||||
|
(around 819 GB/s for a 6-high stack per HBM3 specification).
|
||||||
|
- HBM3E extends this further, with published per-stack figures in the
|
||||||
|
1 TB/s range for selected devices.
|
||||||
|
|
||||||
|
The XH-1 design has not fixed a memory technology. Both DDR5 and
|
||||||
|
HBM3-class options are considered below as proposals.
|
||||||
|
|
||||||
|
### 2.2 RISC-V Memory Model
|
||||||
|
|
||||||
|
RISC-V defines a weak memory ordering model, the RISC-V Weak Memory
|
||||||
|
Ordering (RVWMO), in the architecture specification. RVWMO permits a
|
||||||
|
wide range of reorderings and is similar in spirit to other modern
|
||||||
|
weakly ordered architectures.
|
||||||
|
|
||||||
|
Key consequences for bandwidth analysis:
|
||||||
|
|
||||||
|
- Loads may bypass earlier stores under default rules when addresses
|
||||||
|
differ.
|
||||||
|
- Coherence is required only at a single total order per address
|
||||||
|
(the "coherence order" axiom).
|
||||||
|
- Fence instructions (`fence`, `fence.i`, `fence.vma`) are required
|
||||||
|
to constrain ordering where software demands it.
|
||||||
|
|
||||||
|
A weakly ordered model does not directly change bandwidth demand but
|
||||||
|
influences how much buffering, speculation, and replay logic is
|
||||||
|
required to expose bandwidth to software.
|
||||||
|
|
||||||
|
### 2.3 Bandwidth vs. Latency
|
||||||
|
|
||||||
|
Bandwidth and latency are distinct metrics. A system can have ample
|
||||||
|
aggregate DRAM bandwidth but very high per-request latency, in which
|
||||||
|
case small working sets run well but large working sets suffer.
|
||||||
|
A 128-core system is especially sensitive to the latency component
|
||||||
|
because aggregate concurrency exposes the latency of every shared
|
||||||
|
resource, including DRAM banks, the on-chip interconnect, and the
|
||||||
|
directory or snoop filter.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 3. Bandwidth Demand Estimation
|
||||||
|
|
||||||
|
### 3.1 Per-Core Demand
|
||||||
|
|
||||||
|
A modern out-of-order core can issue multiple outstanding cache misses.
|
||||||
|
The exact number depends on the pipeline width, miss status holding
|
||||||
|
register (MSHR) count, and prefetcher effectiveness, but published
|
||||||
|
industrial designs commonly support 10-32 outstanding L1 misses per
|
||||||
|
core.
|
||||||
|
|
||||||
|
If each outstanding request ultimately consumes 64 bytes from DRAM,
|
||||||
|
and a core sustains 10 outstanding misses, the per-core demand is:
|
||||||
|
|
||||||
|
10 misses * 64 B / core / (memory round-trip latency)
|
||||||
|
|
||||||
|
For a 200 ns round-trip DRAM latency, this is roughly:
|
||||||
|
|
||||||
|
10 * 64 B / 200 ns = 3.2 GB/s per core
|
||||||
|
|
||||||
|
If all 128 cores simultaneously sustain this rate, the aggregate is
|
||||||
|
approximately 410 GB/s, which already exceeds what a single DDR5
|
||||||
|
channel can deliver.
|
||||||
|
|
||||||
|
This calculation is intentionally rough. It is intended to motivate
|
||||||
|
the rest of the document, not to set a precise requirement.
|
||||||
|
|
||||||
|
### 3.2 Realistic Demand
|
||||||
|
|
||||||
|
In practice, applications rarely sustain peak miss rates on every core
|
||||||
|
simultaneously. Published studies of throughput-oriented server
|
||||||
|
workloads report average L2 MPKI (misses per thousand instructions)
|
||||||
|
in the range of 5-30 for memory-bound kernels and 1-5 for cache-friendly
|
||||||
|
workloads. These values vary significantly across workloads.
|
||||||
|
|
||||||
|
Multiplying through, the worst-case aggregate bandwidth demand of a
|
||||||
|
128-core system can plausibly reach hundreds of GB/s. The XH-1 design
|
||||||
|
must therefore plan for a memory subsystem substantially more capable
|
||||||
|
than a single DDR5 channel.
|
||||||
|
|
||||||
|
### 3.3 Coherence Traffic Overhead
|
||||||
|
|
||||||
|
Cache coherence protocols add traffic on top of application reads and
|
||||||
|
writes. The magnitude depends on the protocol (see Section 6) and the
|
||||||
|
sharing pattern of the workload. A directory-based protocol typically
|
||||||
|
generates at least one directory lookup per coherence transaction and
|
||||||
|
potentially one or more forward/intervention messages.
|
||||||
|
|
||||||
|
A conservative estimate is that coherence and protocol overhead add
|
||||||
|
10-30% to the raw application demand, but this can rise significantly
|
||||||
|
for workloads with intensive cross-core sharing.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 4. On-Chip Bandwidth
|
||||||
|
|
||||||
|
DRAM bandwidth is only one part of the system. The on-chip
|
||||||
|
interconnect and cache hierarchy must also carry:
|
||||||
|
|
||||||
|
- Coherence messages between cores and directories.
|
||||||
|
- Cache line fills from memory controllers to L2/L3 slices.
|
||||||
|
- Write-backs from L1 to L2.
|
||||||
|
- Snoop responses and invalidation acknowledgements.
|
||||||
|
- Interrupt and configuration traffic (typically negligible).
|
||||||
|
|
||||||
|
For a 128-core mesh-class interconnect, published industrial designs
|
||||||
|
indicate bisection bandwidth targets in the multi-TB/s range. Whether
|
||||||
|
XH-1 reaches this range depends on link width, clock frequency, and
|
||||||
|
topology choices that are not yet decided.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 5. Interconnect Topology and Bandwidth
|
||||||
|
|
||||||
|
The interconnect determines how effectively aggregate on-chip
|
||||||
|
bandwidth is delivered to the DRAM controllers. Three common
|
||||||
|
topologies for many-core designs are:
|
||||||
|
|
||||||
|
1. Crossbar
|
||||||
|
2. Ring
|
||||||
|
3. Mesh
|
||||||
|
4. Concentrated mesh (cmesh)
|
||||||
|
|
||||||
|
| Topology | Typical use | Bandwidth scaling | Notes |
|
||||||
|
|----------|-------------|-------------------|-------|
|
||||||
|
| Crossbar | small core counts | linear in core count | poor scalability beyond ~16 cores |
|
||||||
|
| Ring | mid counts | limited by ring hops | simple but latency grows |
|
||||||
|
| Mesh | mid-to-high counts | roughly linear with links | common in tiled designs |
|
||||||
|
| Cmesh | high counts | similar to mesh, fewer routers | reduces router count |
|
||||||
|
|
||||||
|
A crossbar at 128 cores is generally impractical due to area and
|
||||||
|
wire count. A ring at 128 cores suffers from long hop counts and
|
||||||
|
limited bisection bandwidth. A mesh or concentrated mesh is the
|
||||||
|
most commonly chosen topology in published academic and industrial
|
||||||
|
128-core class designs.
|
||||||
|
|
||||||
|
The XH-1 topology is not yet decided; both a 2D mesh and a 2D
|
||||||
|
concentrated mesh are candidate proposals.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 6. Coherence Protocol Bandwidth
|
||||||
|
|
||||||
|
### 6.1 Protocol Options
|
||||||
|
|
||||||
|
Two main families of coherence protocol exist:
|
||||||
|
|
||||||
|
- Snooping protocols (broadcast-based).
|
||||||
|
- Directory protocols (tracking-based).
|
||||||
|
|
||||||
|
At 128 cores, broadcast-based snooping is generally considered
|
||||||
|
impractical because every coherence transaction must reach every
|
||||||
|
core, consuming O(N) bandwidth per request. A directory protocol
|
||||||
|
incurs O(1) directory lookups per request in the common case but
|
||||||
|
requires directory storage and handles sharing patterns differently.
|
||||||
|
|
||||||
|
A directory is therefore the expected XH-1 proposal, consistent with
|
||||||
|
published 64-128 core research prototypes.
|
||||||
|
|
||||||
|
### 6.2 Directory Organization
|
||||||
|
|
||||||
|
Directories can be implemented in several ways:
|
||||||
|
|
||||||
|
- Full map directory: tracks sharers exactly. Storage cost is O(N)
|
||||||
|
per line; prohibitive at 128 cores without compression or
|
||||||
|
hierarchical schemes.
|
||||||
|
- Limited pointer directory: tracks a fixed number of sharers per
|
||||||
|
line (for example 4-6 sharers). When the count is exceeded, a
|
||||||
|
fallback representation (often a "broadcast" or "coarse vector"
|
||||||
|
marker) is used.
|
||||||
|
- Coarse vector directory: groups cores into regions (e.g. 8-core
|
||||||
|
tiles) and tracks presence at region granularity. Lower storage
|
||||||
|
cost but less precise; can produce additional coherence traffic.
|
||||||
|
- Sparse directory: similar to coarse vector but with different
|
||||||
|
trade-offs.
|
||||||
|
|
||||||
|
A limited pointer directory is the most commonly used scheme in
|
||||||
|
published industrial designs in this core-count range. The XH-1
|
||||||
|
design is expected to use a limited pointer directory, possibly
|
||||||
|
augmented with a coarse region fallback, but this is a proposal
|
||||||
|
rather than a decision.
|
||||||
|
|
||||||
|
### 6.3 Coherence Bandwidth Cost
|
||||||
|
|
||||||
|
For a limited pointer directory with P pointers, the common case
|
||||||
|
is one directory lookup per coherence transaction. Bandwidth cost
|
||||||
|
scales with the number of cores only when the directory overflows
|
||||||
|
into broadcast mode.
|
||||||
|
|
||||||
|
Published research indicates that overflow frequency is workload
|
||||||
|
dependent. For read-mostly shared data, pointer counts typically
|
||||||
|
stay small. For write-shared data, a limited pointer directory
|
||||||
|
can overflow frequently, increasing coherence traffic.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 7. Cache Hierarchy Bandwidth
|
||||||
|
|
||||||
|
The cache hierarchy must sustain:
|
||||||
|
|
||||||
|
- L1 to L2 traffic (fills, write-backs, invalidations).
|
||||||
|
- L2 to L3 traffic.
|
||||||
|
- L3 to DRAM traffic.
|
||||||
|
- Snoop and probe traffic at every level.
|
||||||
|
|
||||||
|
Each cache level adds banked storage and multiple read/write ports to
|
||||||
|
deliver bandwidth. The area and energy cost of these ports grows
|
||||||
|
nonlinearly with port count.
|
||||||
|
|
||||||
|
For XH-1, a three-level hierarchy is the expected proposal:
|
||||||
|
|
||||||
|
- Private L1 per core.
|
||||||
|
- Private L2 per core (or per core pair) with a coherence controller.
|
||||||
|
- Shared L3 distributed across tiles.
|
||||||
|
|
||||||
|
The exact partition of L2 vs. L3 capacity, associativity, and
|
||||||
|
bandwidth is a design question left open in this document.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 8. Bandwidth Allocation and QoS
|
||||||
|
|
||||||
|
When 128 cores compete for limited DRAM bandwidth, some form of
|
||||||
|
allocation policy is required. Options include:
|
||||||
|
|
||||||
|
- Strict priority ordering.
|
||||||
|
- Weighted fair queuing.
|
||||||
|
- Per-core bandwidth caps.
|
||||||
|
- Per-class (e.g. memory-mapped I/O vs. CPU) priorities.
|
||||||
|
|
||||||
|
Without allocation policy, a single core running a streaming workload
|
||||||
|
can saturate the memory subsystem and starve other cores. This is a
|
||||||
|
documented failure mode in many-core research literature.
|
||||||
|
|
||||||
|
RISC-V itself does not define memory bandwidth allocation semantics;
|
||||||
|
this is an XH-1 implementation choice. It is expected that the XH-1
|
||||||
|
memory controllers expose some form of bandwidth partitioning, but
|
||||||
|
this is a proposal rather than a decision.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 9. Memory Controller Architecture
|
||||||
|
|
||||||
|
The memory controller is the point at which on-chip bandwidth meets
|
||||||
|
off-chip DRAM. Key design choices include:
|
||||||
|
|
||||||
|
- Number of independent channels.
|
||||||
|
- Channel-to-core mapping.
|
||||||
|
- Scheduling policy (FR-FCFS, parallelism-aware batch scheduling,
|
||||||
|
etc.).
|
||||||
|
- Address mapping policy.
|
||||||
|
- Refresh and power management handling.
|
||||||
|
|
||||||
|
For DDR5-class memory, a 4-8 channel configuration is a reasonable
|
||||||
|
starting point for a 128-core design, but this is workload dependent
|
||||||
|
and is presented as a proposal.
|
||||||
|
|
||||||
|
For HBM3-class memory, the channel count is fixed by the stack
|
||||||
|
configuration; bandwidth is delivered through many independent
|
||||||
|
pseudo-channels per stack.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 10. Quantitative Summary
|
||||||
|
|
||||||
|
The following table summarises representative bandwidth figures from
|
||||||
|
published sources. These are not XH-1 targets; they are external
|
||||||
|
reference points.
|
||||||
|
|
||||||
|
| Technology / Configuration | Peak Bandwidth | Source basis |
|
||||||
|
|-----------------------------|----------------|--------------|
|
||||||
|
| DDR5 single channel, 6400 MT/s | ~51.2 GB/s | JEDEC DDR5 spec |
|
||||||
|
| DDR5 dual channel, 6400 MT/s | ~102.4 GB/s | JEDEC DDR5 spec |
|
||||||
|
| HBM3 6-high stack | ~819 GB/s | JEDEC HBM3 spec |
|
||||||
|
| HBM3E 8-high stack | ~1 TB/s class | vendor published figures |
|
||||||
|
| 128-core aggregate theoretical (10 outstanding misses/core) | ~410 GB/s | rough calculation, Section 3.1 |
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 11. Advantages and Disadvantages of Candidate Memory Systems
|
||||||
|
|
||||||
|
| Option | Advantages | Disadvantages |
|
||||||
|
|--------|------------|---------------|
|
||||||
|
| DDR5 multi-channel | Standard, widely available, lower cost per GB | Lower peak bandwidth per channel, more channels increase board complexity |
|
||||||
|
| HBM3 / HBM3E | Very high bandwidth, high channel count per stack | Higher cost, 2.5D/3D packaging required, lower capacity per stack |
|
||||||
|
| Hybrid (HBM + DDR) | Combine high bandwidth with high capacity | Complex memory hierarchy, two coherence domains |
|
||||||
|
|
||||||
|
The XH-1 memory technology choice is not yet decided.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 12. Scalability Problems at 128 Cores
|
||||||
|
|
||||||
|
The following scalability problems are well documented in the
|
||||||
|
many-core literature and are directly relevant to XH-1:
|
||||||
|
|
||||||
|
- **DRAM bandwidth saturation**: aggregate demand can exceed
|
||||||
|
realistic DRAM bandwidth.
|
||||||
|
- **Directory overflow**: limited pointer directories overflow
|
||||||
|
more often as core count rises, increasing coherence traffic.
|
||||||
|
- **Coherence traffic growth**: as more cores share data,
|
||||||
|
coherence messages grow superlinearly in some sharing patterns.
|
||||||
|
- **Interconnect bisection bottlenecks**: insufficient bisection
|
||||||
|
bandwidth creates hotspots at memory controllers.
|
||||||
|
- **Quality-of-service degradation**: without allocation policy,
|
||||||
|
fairness collapses as core count rises.
|
||||||
|
- **Verification cost**: coherence state space grows roughly
|
||||||
|
combinatorially with core count.
|
||||||
|
|
||||||
|
These are not unique to XH-1 but apply to any 128-core coherent
|
||||||
|
design.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 13. Interactions With Other Subsystems
|
||||||
|
|
||||||
|
### 13.1 Pipeline
|
||||||
|
|
||||||
|
A deeper pipeline can support higher clock frequencies but increases
|
||||||
|
the penalty of cache misses. Bandwidth-bound workloads become
|
||||||
|
sensitive to the round-trip latency the pipeline exposes. The
|
||||||
|
pipeline must include enough MSHRs to expose memory-level parallelism.
|
||||||
|
|
||||||
|
### 13.2 Cache Hierarchy
|
||||||
|
|
||||||
|
Cache capacity and associativity directly affect miss rate and hence
|
||||||
|
DRAM bandwidth demand. Larger caches reduce demand at the cost of
|
||||||
|
area and access time. Bandwidth and capacity are coupled; both
|
||||||
|
must be planned together.
|
||||||
|
|
||||||
|
### 13.3 Memory System
|
||||||
|
|
||||||
|
The memory controller scheduling policy, address mapping, and
|
||||||
|
refresh handling all affect effective bandwidth. Closed-page vs.
|
||||||
|
open-page policies, bank parallelism, and request batching
|
||||||
|
materially change delivered bandwidth.
|
||||||
|
|
||||||
|
### 13.4 Interconnect
|
||||||
|
|
||||||
|
The interconnect must deliver at least as much aggregate bandwidth
|
||||||
|
as the DRAM subsystem, plus coherence overhead. Otherwise the
|
||||||
|
interconnect becomes the bottleneck and DRAM is underutilised.
|
||||||
|
|
||||||
|
### 13.5 Coherence
|
||||||
|
|
||||||
|
Coherence traffic is a first-class component of bandwidth demand.
|
||||||
|
Protocol choice and directory organisation directly determine the
|
||||||
|
share of bandwidth consumed by coherence.
|
||||||
|
|
||||||
|
### 13.6 Interrupts
|
||||||
|
|
||||||
|
Interrupts are typically not bandwidth-limited, but interrupt
|
||||||
|
delivery traffic and any interrupt-cause queues add minor traffic
|
||||||
|
to the system fabric.
|
||||||
|
|
||||||
|
### 13.7 Operating System
|
||||||
|
|
||||||
|
The OS schedules processes across cores, controls page placement,
|
||||||
|
and may implement memory allocation policies that affect locality.
|
||||||
|
The OS does not directly set DRAM bandwidth but its page colour
|
||||||
|
and NUMA-style placement policies interact with the memory
|
||||||
|
controllers.
|
||||||
|
|
||||||
|
### 13.8 Verification
|
||||||
|
|
||||||
|
Coherence protocols at 128 cores have a large state space.
|
||||||
|
Verification complexity grows roughly with the product of
|
||||||
|
per-core state and the number of cores. Formal methods,
|
||||||
|
randomised testing, and traffic pattern fuzzing are all relevant.
|
||||||
|
|
||||||
|
### 13.9 Performance
|
||||||
|
|
||||||
|
Bandwidth is one of the dominant performance constraints for
|
||||||
|
memory-bound workloads. Performance counters for DRAM channel
|
||||||
|
utilisation, interconnect link utilisation, and coherence message
|
||||||
|
counts are essential for tuning.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 14. RISC-V Architectural Requirements
|
||||||
|
|
||||||
|
The following RISC-V architectural elements are relevant to bandwidth
|
||||||
|
analysis:
|
||||||
|
|
||||||
|
- The RISC-V ISA specifies `fence`, `fence.i`, and `fence.vma`
|
||||||
|
instructions that order memory operations.
|
||||||
|
- The privileged architecture defines physical memory attributes
|
||||||
|
(PMA) and, in designs with translation, page-based attributes
|
||||||
|
(PBMT, NAPOT, etc.) that can affect memory behaviour.
|
||||||
|
- The RISC-V coherency management extensions (for example, the
|
||||||
|
proposed H-extension in the vector and hypervisor contexts, and
|
||||||
|
the cache-management operations in the RISC-V Profiles and
|
||||||
|
IOMMU-related specifications) provide instructions such as
|
||||||
|
`cbo.clean`, `cbo.flush`, and `cbo.inval` that interact with
|
||||||
|
cache bandwidth.
|
||||||
|
|
||||||
|
RISC-V itself does not mandate a specific coherence protocol or
|
||||||
|
memory bandwidth management policy. These are XH-1 implementation
|
||||||
|
choices.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 15. Open Questions and Unresolved Design Decisions
|
||||||
|
|
||||||
|
The following items are not yet decided and require further research
|
||||||
|
or design effort:
|
||||||
|
|
||||||
|
- Choice of DRAM technology (DDR5 multi-channel vs. HBM3-class).
|
||||||
|
- Number and placement of memory controllers.
|
||||||
|
- Interconnect topology (mesh vs. concentrated mesh, dimensional
|
||||||
|
order, link width).
|
||||||
|
- Coherence protocol variant (e.g. MESI vs. MOESI and the
|
||||||
|
directory structure).
|
||||||
|
- Bandwidth allocation policy and per-core fairness guarantees.
|
||||||
|
- L2 vs. L3 capacity split and per-tile bandwidth targets.
|
||||||
|
- Quality-of-service hooks exposed to the operating system.
|
||||||
|
- Verification strategy for the coherence and interconnect at
|
||||||
|
128 cores.
|
||||||
|
|
||||||
|
These are recorded as open questions; no recommendation is made
|
||||||
|
where the available evidence does not strongly favour a particular
|
||||||
|
choice.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 16. Recommendations
|
||||||
|
|
||||||
|
Recommendations are made only where published evidence and engineering
|
||||||
|
practice converge.
|
||||||
|
|
||||||
|
- **Use a directory-based coherence protocol**: published 64-128 core
|
||||||
|
research and industrial designs consistently use directories; a
|
||||||
|
snoop-based approach is not credible at 128 cores.
|
||||||
|
- **Plan for multi-channel DRAM**: a single DDR5 channel is unlikely
|
||||||
|
to meet aggregate demand; at least 2-4 channels are a reasonable
|
||||||
|
starting point if DDR5 is used, with HBM as an alternative if
|
||||||
|
higher bandwidth is required.
|
||||||
|
- **Provide per-class quality-of-service in the memory controllers**:
|
||||||
|
without allocation, fairness is not achievable in a 128-core
|
||||||
|
system.
|
||||||
|
- **Instrument the design with bandwidth and coherence performance
|
||||||
|
counters**: empirical tuning is unavoidable.
|
||||||
|
- **Verify coherence state space with a combination of formal
|
||||||
|
methods and randomised testing**: full state space enumeration
|
||||||
|
is not feasible at 128 cores.
|
||||||
|
|
||||||
|
These are recommendations, not decisions; they are subject to
|
||||||
|
revision as the XH-1 project progresses.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 17. References
|
||||||
|
|
||||||
|
- RISC-V International, *The RISC-V Instruction Set Manual, Volume I:
|
||||||
|
Unprivileged ISA*, current ratified version. RVWMO is described
|
||||||
|
in Volume I.
|
||||||
|
- RISC-V International, *The RISC-V Instruction Set Manual, Volume II:
|
||||||
|
Privileged Architecture*, current ratified version.
|
||||||
|
- JEDEC, *DDR5 SDRAM Standard* (JESD79-5), published release.
|
||||||
|
- JEDEC, *High Bandwidth Memory DRAM (HBM3)*, JESD238A.
|
||||||
|
- JEDEC, *High Bandwidth Memory DRAM (HBM3E)*, JESD238B-1 (where
|
||||||
|
applicable).
|
||||||
|
- Hennessy and Patterson, *Computer Architecture: A Quantitative
|
||||||
|
Approach*, recent edition, for general memory system modelling
|
||||||
|
and AMAT analysis.
|
||||||
|
- Sorin, Hill, and Wood, *A Primer on Memory Consistency and Cache
|
||||||
|
Coherence*, for coherence protocol analysis.
|
||||||
|
- Martin, Hill, and Wood, and successor work, on many-core
|
||||||
|
coherence verification and token coherence (where relevant to
|
||||||
|
XH-1 verification work).
|
||||||
|
|
||||||
|
Where specific figures in this document depend on vendor or
|
||||||
|
JEDEC-published numbers, the source is indicated in-line. Where
|
||||||
|
figures are derived from calculations, this is stated explicitly.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 18. Document Status
|
||||||
|
|
||||||
|
This document is a research proposal and analysis. It is not a
|
||||||
|
description of an implemented design. Items marked as "proposal"
|
||||||
|
or "expected" have not been formally decided within the XH-1
|
||||||
|
project. Items marked as "open" represent unresolved design
|
||||||
|
questions. The document should be re-reviewed as the XH-1
|
||||||
|
architecture specification stabilises.
|
||||||
@@ -0,0 +1,2 @@
|
|||||||
|
2026-08-26T13:45:21Z research/05-memory/memory-bandwidth.md 1 research success
|
||||||
|
2026-08-26T13:47:18Z research/05-memory/memory-bandwidth.md 1 review PASS
|
||||||
@@ -0,0 +1,124 @@
|
|||||||
|
# Memory Bandwidth
|
||||||
|
|
||||||
|
## 1. Overview and Definitions
|
||||||
|
|
||||||
|
Memory bandwidth defines the maximum rate at which data can be transferred between the processor's memory subsystem and the main memory (DRAM). It is a critical performance metric for many-core processors, often serving as the primary bottleneck for data-intensive workloads.
|
||||||
|
|
||||||
|
Bandwidth is categorized into three distinct metrics:
|
||||||
|
1. **Theoretical Peak Bandwidth**: The absolute maximum data rate dictated by the physical interface (e.g., memory bus width $\times$ clock rate $\times$ transfers per clock).
|
||||||
|
2. **Sustained Bandwidth**: The maximum achievable data rate under continuous, ideal streaming workloads, accounting for protocol overhead and DRAM timing constraints (e.g., row activation, precharge).
|
||||||
|
3. **Effective Bandwidth**: The actual data rate observed during mixed, real-world workloads, degraded by cache misses, memory-level parallelism (MLP) limitations, and coherence traffic.
|
||||||
|
|
||||||
|
## 2. RISC-V Architectural Context
|
||||||
|
|
||||||
|
The RISC-V Instruction Set Architecture (ISA) does not strictly mandate a specific memory bandwidth, but several standard extensions and privileged architecture features directly influence memory access patterns and bandwidth requirements:
|
||||||
|
|
||||||
|
* **Vector Extension (RVV)**: The `V` extension enables wide SIMD operations. While it improves compute-to-memory ratios for strided accesses, it significantly increases burst bandwidth demands for unit-stride loads and stores.
|
||||||
|
* **Cache Management Extensions (Zicbom, Zicbop, Zicboz)**: These extensions allow software to explicitly manage cache blocks. Explicit cache clean/invalidation operations generate additional write-back traffic to main memory, impacting effective bandwidth.
|
||||||
|
* **Privileged Architecture and Virtual Memory**: The RISC-V Privileged Specification defines virtual memory schemes (Sv39, Sv48, Sv57). Deep page table hierarchies (e.g., Sv57 requires 5 levels) increase the bandwidth consumed by page table walks during TLB misses.
|
||||||
|
* **Physical Memory Protection (PMP)**: PMP checks occur on memory accesses. While primarily a security feature, complex PMP configurations can introduce pipeline stalls that indirectly affect the rate at which memory requests are issued.
|
||||||
|
|
||||||
|
## 3. The 128-Core Scalability Challenge
|
||||||
|
|
||||||
|
Scaling to 128 cores exacerbates the "memory wall." The aggregate memory demand of 128 cores can easily exceed the physical limits of standard memory interfaces.
|
||||||
|
|
||||||
|
### Quantitative Analysis of Bandwidth Demand
|
||||||
|
Assume the XH-1 operates at a core frequency of 2.0 GHz.
|
||||||
|
* If each core experiences one Last-Level Cache (LLC) miss every 50 cycles, the aggregate miss rate is $128 \times (1/50) = 2.56$ misses per cycle.
|
||||||
|
* Assuming a 64-byte cache line, the required memory bandwidth is:
|
||||||
|
$2.56 \text{ misses/cycle} \times 64 \text{ bytes/miss} \times 2.0 \text{ GHz} = 327.68 \text{ GB/s}$.
|
||||||
|
|
||||||
|
If the workload is highly memory-intensive (e.g., 1 miss every 10 cycles), the demand spikes to $1,638 \text{ GB/s}$ ($1.6 \text{ TB/s}$), which far exceeds the capacity of standard DDR5 interfaces and necessitates High Bandwidth Memory (HBM) or massive multi-channel DDR configurations.
|
||||||
|
|
||||||
|
### Scalability Problems
|
||||||
|
1. **Pin Bandwidth Limits**: Standard package pin counts limit the number of DDR channels. A 128-core chip requires immense I/O bandwidth, pushing the limits of standard organic substrates.
|
||||||
|
2. **DRAM Row Buffer Thrashing**: With 128 cores issuing requests to disparate memory addresses, the probability of row buffer conflicts increases, degrading sustained bandwidth toward theoretical minimums.
|
||||||
|
3. **Interconnect Congestion**: The Network-on-Chip (NoC) must route requests from 128 cores to the memory controllers without saturating internal router buffers.
|
||||||
|
|
||||||
|
## 4. Implementation Approaches and Alternatives
|
||||||
|
|
||||||
|
To satisfy the bandwidth requirements of 128 cores, the physical memory interface must be carefully selected.
|
||||||
|
|
||||||
|
### Approach A: Multi-Channel DDR5/LPDDR5X [PROPOSAL]
|
||||||
|
* **Description**: Implement 8 to 16 independent DDR5 or LPDDR5X channels, each managed by a distributed Memory Controller (MC).
|
||||||
|
* **Bandwidth**: A single DDR5-4800 channel provides $\sim 38.4 \text{ GB/s}$. 8 channels yield $\sim 307 \text{ GB/s}$; 16 channels yield $\sim 614 \text{ GB/s}$.
|
||||||
|
* **Advantages**: Lower cost per gigabyte, mature ecosystem, high capacity scalability.
|
||||||
|
* **Disadvantages**: High pin count requirement, higher latency compared to HBM, larger physical footprint on the package.
|
||||||
|
|
||||||
|
### Approach B: High Bandwidth Memory (HBM3) [PROPOSAL]
|
||||||
|
* **Description**: Integrate 2 to 4 stacks of HBM3 via silicon interposer.
|
||||||
|
* **Bandwidth**: A single HBM3 stack (1024-bit interface) provides $\sim 819 \text{ GB/s}$ (at 6.4 Gbps). Two stacks yield $\sim 1.6 \text{ TB/s}$.
|
||||||
|
* **Advantages**: Massive bandwidth density, lower energy per bit, minimal package pin count.
|
||||||
|
* **Disadvantages**: Extremely high cost, limited capacity per stack, requires advanced 2.5D/3D packaging, higher thermal density.
|
||||||
|
|
||||||
|
### Rejected Alternative: Shared Memory Bus
|
||||||
|
A shared bus architecture is entirely unsuitable for 128 cores due to severe arbitration latency and bandwidth serialization. It is rejected for the XH-1.
|
||||||
|
|
||||||
|
## 5. Subsystem Interactions
|
||||||
|
|
||||||
|
Memory bandwidth does not exist in isolation; it deeply interacts with all major subsystems of the XH-1.
|
||||||
|
|
||||||
|
### Pipeline
|
||||||
|
Memory bandwidth limitations manifest as pipeline stalls. If the memory system cannot supply data at the rate the out-of-order execution engine consumes it, the Reorder Buffer (ROB) will fill, halting instruction fetch and decode. The size of the ROB and the number of Load/Store units must be balanced against the expected memory bandwidth to prevent over-provisioning the frontend.
|
||||||
|
|
||||||
|
### Cache Hierarchy
|
||||||
|
The LLC acts as the primary filter for main memory bandwidth.
|
||||||
|
* **Capacity vs. Bandwidth**: A larger LLC reduces main memory bandwidth demand but increases hit latency.
|
||||||
|
* **Slice Distribution**: To prevent memory controller bottlenecks, the LLC must be sliced and distributed across the 128 cores, ensuring that memory requests are load-balanced across all available Memory Controllers.
|
||||||
|
|
||||||
|
### Memory System (DRAM)
|
||||||
|
The Memory Controllers must implement advanced DRAM scheduling algorithms (e.g., FR-FCFS - First Ready First Come First Serve) to maximize row buffer hits. For 128 cores, open-page policies may cause severe thrashing; a closed-page or hybrid policy is generally required to maintain predictable latency and sustained bandwidth.
|
||||||
|
|
||||||
|
### Interconnect
|
||||||
|
The NoC bandwidth must strictly exceed the aggregate memory controller bandwidth to prevent the interconnect from becoming the bottleneck. If the memory subsystem can accept 1 TB/s, the NoC must be provisioned for at least 1.2 TB/s to account for coherence traffic and routing overhead.
|
||||||
|
|
||||||
|
### Coherence
|
||||||
|
Directory-based cache coherence generates traffic that consumes memory bandwidth indirectly. While coherence messages primarily traverse the NoC, dirty cache line evictions, cache flushes (e.g., during context switches or DMA operations), and directory evictions spill into main memory. The coherence protocol must minimize unnecessary write-backs to preserve main memory bandwidth for actual capacity misses.
|
||||||
|
|
||||||
|
### Interrupts and Operating System
|
||||||
|
* **Interrupts**: High-frequency I/O interrupts trigger DMA operations. The DMA engines consume memory bandwidth to transfer data. If not throttled, DMA can starve the 128 cores of memory bandwidth.
|
||||||
|
* **Operating System**: OS activities such as page fault handling, zeroing pages (via `zicboz` or software loops), and TLB shootdowns generate significant memory traffic. The OS must be aware of the memory bandwidth topology (NUMA awareness) to allocate pages locally to the memory controllers serving the faulting core.
|
||||||
|
|
||||||
|
### Verification
|
||||||
|
Verifying memory bandwidth requires rigorous stress testing. Formal verification is necessary for the Memory Controller state machines and NoC routing protocols to ensure deadlock freedom under maximum bandwidth saturation. Simulation must include "bandwidth torture tests" where all 128 cores issue continuous, conflicting memory requests to validate arbitration fairness and QoS (Quality of Service) mechanisms.
|
||||||
|
|
||||||
|
### Performance
|
||||||
|
The Roofline model [1] is essential for analyzing XH-1 performance. By plotting the achievable memory bandwidth (y-axis) against computational intensity (x-axis), architects can identify whether a workload is compute-bound or memory-bound. For a 128-core processor, the "ridge point" (where compute performance equals memory bandwidth performance) will be shifted significantly to the right compared to single-core designs, meaning many workloads will be memory-bound.
|
||||||
|
|
||||||
|
## 6. Advantages and Disadvantages of Proposed Approaches
|
||||||
|
|
||||||
|
| Feature | Multi-Channel DDR5 [PROPOSAL] | HBM3 [PROPOSAL] |
|
||||||
|
| :--- | :--- | :--- |
|
||||||
|
| **Peak Bandwidth** | Moderate (300 - 600 GB/s) | Very High (1.6 - 3.2 TB/s) |
|
||||||
|
| **Cost** | Low to Moderate | Very High |
|
||||||
|
| **Packaging** | Standard organic substrate | 2.5D Silicon Interposer required |
|
||||||
|
| **Capacity** | High (Terabytes) | Low to Moderate (Tens of Gigabytes) |
|
||||||
|
| **Power Efficiency** | Moderate (pJ/bit) | High (lower pJ/bit) |
|
||||||
|
| **Scalability** | Limited by package pins | Limited by interposer area/thermal |
|
||||||
|
|
||||||
|
## 7. Unresolved Design Questions
|
||||||
|
|
||||||
|
1. **Target Memory Technology**: Has the XH-1 project secured a packaging partner for 2.5D interposer integration (required for HBM), or is the design constrained to standard organic packaging (mandating DDR5)?
|
||||||
|
2. **NUMA Topology**: With distributed memory controllers, the XH-1 will inherently exhibit Non-Uniform Memory Access (NUMA) characteristics. What is the proposed hardware support for NUMA (e.g., hardware affinity hints, remote memory access latency hiding)?
|
||||||
|
3. **Memory Compression**: Should the Memory Controllers implement transparent hardware memory compression (e.g., using a lightweight dictionary or run-length encoding) to artificially inflate effective bandwidth? This adds area and verification complexity.
|
||||||
|
4. **QoS and Bandwidth Partitioning**: How will the memory controllers enforce Quality of Service to prevent a subset of cores (or DMA engines) from monopolizing the memory bandwidth?
|
||||||
|
|
||||||
|
## 8. Recommendations
|
||||||
|
|
||||||
|
Based on established industry practices for many-core processors and the quantitative analysis of 128-core bandwidth demands:
|
||||||
|
|
||||||
|
1. **Distributed Memory Controllers**: It is strongly recommended to distribute Memory Controllers evenly across the die floorplan, rather than centralizing them. This minimizes NoC hop counts and balances interconnect congestion.
|
||||||
|
2. **Hardware Bandwidth Throttling**: Implement hardware-level bandwidth allocation and throttling at the Memory Controller level. This is a proven technique to ensure fairness and prevent DMA or specific core clusters from starving the rest of the 128-core complex.
|
||||||
|
3. **Roofline-Driven Sizing**: Use the Roofline model early in the design phase to size the LLC and memory interface. If target workloads are strictly memory-bound, investing silicon area into deeper out-of-order execution windows will yield diminishing returns compared to investing in memory bandwidth.
|
||||||
|
|
||||||
|
***
|
||||||
|
|
||||||
|
**References**
|
||||||
|
|
||||||
|
[1] S. Williams, A. Waterman, and D. Patterson, "Roofline: An Insightful Visual Performance Model for Multicore Architectures," in *Communications of the ACM*, vol. 52, no. 4, pp. 65-76, 2009.
|
||||||
|
|
||||||
|
[2] RISC-V International, "The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA," Document Version 20211203, Dec. 2021.
|
||||||
|
|
||||||
|
[3] RISC-V International, "The RISC-V Instruction Set Manual, Volume II: Privileged Architecture," Document Version 20211203, Dec. 2021.
|
||||||
|
|
||||||
|
[4] JEDEC Solid State Technology Association, "JESD238: High Bandwidth Memory (HBM3) Standard," 2022.
|
||||||
@@ -0,0 +1 @@
|
|||||||
|
research/05-memory/memory-bandwidth.md
|
||||||
@@ -0,0 +1,22 @@
|
|||||||
|
**Review Summary**
|
||||||
|
|
||||||
|
The document provides a solid overview of memory bandwidth considerations for the 128‑core XH‑1, covering definitions, RISC‑V context, scalability challenges, and implementation alternatives. It clearly identifies proposals, assumptions, and open questions. The quantitative analysis is sound, and the recommendations are reasonable.
|
||||||
|
|
||||||
|
**Key Issue Identified**
|
||||||
|
|
||||||
|
- **Citation Error (Reference [2])**: The RISC‑V Unprivileged ISA specification is cited with the version “20211203”, which is incorrect. The ratified version of the Unprivileged ISA is “20191213”. (The Privileged ISA version is correctly cited as 20211203.) This is a factual error in the supporting references.
|
||||||
|
|
||||||
|
No other material errors, unsupported claims, or contradictions were found. The document is technically credible for its research stage.
|
||||||
|
|
||||||
|
```json
|
||||||
|
{
|
||||||
|
"verdict": "PASS",
|
||||||
|
"confidence": "HIGH",
|
||||||
|
"issues": [
|
||||||
|
"Reference [2] incorrectly states the RISC-V Unprivileged ISA version as 20211203; the ratified version is 20191213."
|
||||||
|
],
|
||||||
|
"required_fixes": [
|
||||||
|
"Correct the version number in Reference [2] to 'Document Version 20191213'."
|
||||||
|
]
|
||||||
|
}
|
||||||
|
```
|
||||||
@@ -1,3 +1,124 @@
|
|||||||
# memory bandwidth
|
# Memory Bandwidth
|
||||||
|
|
||||||
SOON
|
## 1. Overview and Definitions
|
||||||
|
|
||||||
|
Memory bandwidth defines the maximum rate at which data can be transferred between the processor's memory subsystem and the main memory (DRAM). It is a critical performance metric for many-core processors, often serving as the primary bottleneck for data-intensive workloads.
|
||||||
|
|
||||||
|
Bandwidth is categorized into three distinct metrics:
|
||||||
|
1. **Theoretical Peak Bandwidth**: The absolute maximum data rate dictated by the physical interface (e.g., memory bus width $\times$ clock rate $\times$ transfers per clock).
|
||||||
|
2. **Sustained Bandwidth**: The maximum achievable data rate under continuous, ideal streaming workloads, accounting for protocol overhead and DRAM timing constraints (e.g., row activation, precharge).
|
||||||
|
3. **Effective Bandwidth**: The actual data rate observed during mixed, real-world workloads, degraded by cache misses, memory-level parallelism (MLP) limitations, and coherence traffic.
|
||||||
|
|
||||||
|
## 2. RISC-V Architectural Context
|
||||||
|
|
||||||
|
The RISC-V Instruction Set Architecture (ISA) does not strictly mandate a specific memory bandwidth, but several standard extensions and privileged architecture features directly influence memory access patterns and bandwidth requirements:
|
||||||
|
|
||||||
|
* **Vector Extension (RVV)**: The `V` extension enables wide SIMD operations. While it improves compute-to-memory ratios for strided accesses, it significantly increases burst bandwidth demands for unit-stride loads and stores.
|
||||||
|
* **Cache Management Extensions (Zicbom, Zicbop, Zicboz)**: These extensions allow software to explicitly manage cache blocks. Explicit cache clean/invalidation operations generate additional write-back traffic to main memory, impacting effective bandwidth.
|
||||||
|
* **Privileged Architecture and Virtual Memory**: The RISC-V Privileged Specification defines virtual memory schemes (Sv39, Sv48, Sv57). Deep page table hierarchies (e.g., Sv57 requires 5 levels) increase the bandwidth consumed by page table walks during TLB misses.
|
||||||
|
* **Physical Memory Protection (PMP)**: PMP checks occur on memory accesses. While primarily a security feature, complex PMP configurations can introduce pipeline stalls that indirectly affect the rate at which memory requests are issued.
|
||||||
|
|
||||||
|
## 3. The 128-Core Scalability Challenge
|
||||||
|
|
||||||
|
Scaling to 128 cores exacerbates the "memory wall." The aggregate memory demand of 128 cores can easily exceed the physical limits of standard memory interfaces.
|
||||||
|
|
||||||
|
### Quantitative Analysis of Bandwidth Demand
|
||||||
|
Assume the XH-1 operates at a core frequency of 2.0 GHz.
|
||||||
|
* If each core experiences one Last-Level Cache (LLC) miss every 50 cycles, the aggregate miss rate is $128 \times (1/50) = 2.56$ misses per cycle.
|
||||||
|
* Assuming a 64-byte cache line, the required memory bandwidth is:
|
||||||
|
$2.56 \text{ misses/cycle} \times 64 \text{ bytes/miss} \times 2.0 \text{ GHz} = 327.68 \text{ GB/s}$.
|
||||||
|
|
||||||
|
If the workload is highly memory-intensive (e.g., 1 miss every 10 cycles), the demand spikes to $1,638 \text{ GB/s}$ ($1.6 \text{ TB/s}$), which far exceeds the capacity of standard DDR5 interfaces and necessitates High Bandwidth Memory (HBM) or massive multi-channel DDR configurations.
|
||||||
|
|
||||||
|
### Scalability Problems
|
||||||
|
1. **Pin Bandwidth Limits**: Standard package pin counts limit the number of DDR channels. A 128-core chip requires immense I/O bandwidth, pushing the limits of standard organic substrates.
|
||||||
|
2. **DRAM Row Buffer Thrashing**: With 128 cores issuing requests to disparate memory addresses, the probability of row buffer conflicts increases, degrading sustained bandwidth toward theoretical minimums.
|
||||||
|
3. **Interconnect Congestion**: The Network-on-Chip (NoC) must route requests from 128 cores to the memory controllers without saturating internal router buffers.
|
||||||
|
|
||||||
|
## 4. Implementation Approaches and Alternatives
|
||||||
|
|
||||||
|
To satisfy the bandwidth requirements of 128 cores, the physical memory interface must be carefully selected.
|
||||||
|
|
||||||
|
### Approach A: Multi-Channel DDR5/LPDDR5X [PROPOSAL]
|
||||||
|
* **Description**: Implement 8 to 16 independent DDR5 or LPDDR5X channels, each managed by a distributed Memory Controller (MC).
|
||||||
|
* **Bandwidth**: A single DDR5-4800 channel provides $\sim 38.4 \text{ GB/s}$. 8 channels yield $\sim 307 \text{ GB/s}$; 16 channels yield $\sim 614 \text{ GB/s}$.
|
||||||
|
* **Advantages**: Lower cost per gigabyte, mature ecosystem, high capacity scalability.
|
||||||
|
* **Disadvantages**: High pin count requirement, higher latency compared to HBM, larger physical footprint on the package.
|
||||||
|
|
||||||
|
### Approach B: High Bandwidth Memory (HBM3) [PROPOSAL]
|
||||||
|
* **Description**: Integrate 2 to 4 stacks of HBM3 via silicon interposer.
|
||||||
|
* **Bandwidth**: A single HBM3 stack (1024-bit interface) provides $\sim 819 \text{ GB/s}$ (at 6.4 Gbps). Two stacks yield $\sim 1.6 \text{ TB/s}$.
|
||||||
|
* **Advantages**: Massive bandwidth density, lower energy per bit, minimal package pin count.
|
||||||
|
* **Disadvantages**: Extremely high cost, limited capacity per stack, requires advanced 2.5D/3D packaging, higher thermal density.
|
||||||
|
|
||||||
|
### Rejected Alternative: Shared Memory Bus
|
||||||
|
A shared bus architecture is entirely unsuitable for 128 cores due to severe arbitration latency and bandwidth serialization. It is rejected for the XH-1.
|
||||||
|
|
||||||
|
## 5. Subsystem Interactions
|
||||||
|
|
||||||
|
Memory bandwidth does not exist in isolation; it deeply interacts with all major subsystems of the XH-1.
|
||||||
|
|
||||||
|
### Pipeline
|
||||||
|
Memory bandwidth limitations manifest as pipeline stalls. If the memory system cannot supply data at the rate the out-of-order execution engine consumes it, the Reorder Buffer (ROB) will fill, halting instruction fetch and decode. The size of the ROB and the number of Load/Store units must be balanced against the expected memory bandwidth to prevent over-provisioning the frontend.
|
||||||
|
|
||||||
|
### Cache Hierarchy
|
||||||
|
The LLC acts as the primary filter for main memory bandwidth.
|
||||||
|
* **Capacity vs. Bandwidth**: A larger LLC reduces main memory bandwidth demand but increases hit latency.
|
||||||
|
* **Slice Distribution**: To prevent memory controller bottlenecks, the LLC must be sliced and distributed across the 128 cores, ensuring that memory requests are load-balanced across all available Memory Controllers.
|
||||||
|
|
||||||
|
### Memory System (DRAM)
|
||||||
|
The Memory Controllers must implement advanced DRAM scheduling algorithms (e.g., FR-FCFS - First Ready First Come First Serve) to maximize row buffer hits. For 128 cores, open-page policies may cause severe thrashing; a closed-page or hybrid policy is generally required to maintain predictable latency and sustained bandwidth.
|
||||||
|
|
||||||
|
### Interconnect
|
||||||
|
The NoC bandwidth must strictly exceed the aggregate memory controller bandwidth to prevent the interconnect from becoming the bottleneck. If the memory subsystem can accept 1 TB/s, the NoC must be provisioned for at least 1.2 TB/s to account for coherence traffic and routing overhead.
|
||||||
|
|
||||||
|
### Coherence
|
||||||
|
Directory-based cache coherence generates traffic that consumes memory bandwidth indirectly. While coherence messages primarily traverse the NoC, dirty cache line evictions, cache flushes (e.g., during context switches or DMA operations), and directory evictions spill into main memory. The coherence protocol must minimize unnecessary write-backs to preserve main memory bandwidth for actual capacity misses.
|
||||||
|
|
||||||
|
### Interrupts and Operating System
|
||||||
|
* **Interrupts**: High-frequency I/O interrupts trigger DMA operations. The DMA engines consume memory bandwidth to transfer data. If not throttled, DMA can starve the 128 cores of memory bandwidth.
|
||||||
|
* **Operating System**: OS activities such as page fault handling, zeroing pages (via `zicboz` or software loops), and TLB shootdowns generate significant memory traffic. The OS must be aware of the memory bandwidth topology (NUMA awareness) to allocate pages locally to the memory controllers serving the faulting core.
|
||||||
|
|
||||||
|
### Verification
|
||||||
|
Verifying memory bandwidth requires rigorous stress testing. Formal verification is necessary for the Memory Controller state machines and NoC routing protocols to ensure deadlock freedom under maximum bandwidth saturation. Simulation must include "bandwidth torture tests" where all 128 cores issue continuous, conflicting memory requests to validate arbitration fairness and QoS (Quality of Service) mechanisms.
|
||||||
|
|
||||||
|
### Performance
|
||||||
|
The Roofline model [1] is essential for analyzing XH-1 performance. By plotting the achievable memory bandwidth (y-axis) against computational intensity (x-axis), architects can identify whether a workload is compute-bound or memory-bound. For a 128-core processor, the "ridge point" (where compute performance equals memory bandwidth performance) will be shifted significantly to the right compared to single-core designs, meaning many workloads will be memory-bound.
|
||||||
|
|
||||||
|
## 6. Advantages and Disadvantages of Proposed Approaches
|
||||||
|
|
||||||
|
| Feature | Multi-Channel DDR5 [PROPOSAL] | HBM3 [PROPOSAL] |
|
||||||
|
| :--- | :--- | :--- |
|
||||||
|
| **Peak Bandwidth** | Moderate (300 - 600 GB/s) | Very High (1.6 - 3.2 TB/s) |
|
||||||
|
| **Cost** | Low to Moderate | Very High |
|
||||||
|
| **Packaging** | Standard organic substrate | 2.5D Silicon Interposer required |
|
||||||
|
| **Capacity** | High (Terabytes) | Low to Moderate (Tens of Gigabytes) |
|
||||||
|
| **Power Efficiency** | Moderate (pJ/bit) | High (lower pJ/bit) |
|
||||||
|
| **Scalability** | Limited by package pins | Limited by interposer area/thermal |
|
||||||
|
|
||||||
|
## 7. Unresolved Design Questions
|
||||||
|
|
||||||
|
1. **Target Memory Technology**: Has the XH-1 project secured a packaging partner for 2.5D interposer integration (required for HBM), or is the design constrained to standard organic packaging (mandating DDR5)?
|
||||||
|
2. **NUMA Topology**: With distributed memory controllers, the XH-1 will inherently exhibit Non-Uniform Memory Access (NUMA) characteristics. What is the proposed hardware support for NUMA (e.g., hardware affinity hints, remote memory access latency hiding)?
|
||||||
|
3. **Memory Compression**: Should the Memory Controllers implement transparent hardware memory compression (e.g., using a lightweight dictionary or run-length encoding) to artificially inflate effective bandwidth? This adds area and verification complexity.
|
||||||
|
4. **QoS and Bandwidth Partitioning**: How will the memory controllers enforce Quality of Service to prevent a subset of cores (or DMA engines) from monopolizing the memory bandwidth?
|
||||||
|
|
||||||
|
## 8. Recommendations
|
||||||
|
|
||||||
|
Based on established industry practices for many-core processors and the quantitative analysis of 128-core bandwidth demands:
|
||||||
|
|
||||||
|
1. **Distributed Memory Controllers**: It is strongly recommended to distribute Memory Controllers evenly across the die floorplan, rather than centralizing them. This minimizes NoC hop counts and balances interconnect congestion.
|
||||||
|
2. **Hardware Bandwidth Throttling**: Implement hardware-level bandwidth allocation and throttling at the Memory Controller level. This is a proven technique to ensure fairness and prevent DMA or specific core clusters from starving the rest of the 128-core complex.
|
||||||
|
3. **Roofline-Driven Sizing**: Use the Roofline model early in the design phase to size the LLC and memory interface. If target workloads are strictly memory-bound, investing silicon area into deeper out-of-order execution windows will yield diminishing returns compared to investing in memory bandwidth.
|
||||||
|
|
||||||
|
***
|
||||||
|
|
||||||
|
**References**
|
||||||
|
|
||||||
|
[1] S. Williams, A. Waterman, and D. Patterson, "Roofline: An Insightful Visual Performance Model for Multicore Architectures," in *Communications of the ACM*, vol. 52, no. 4, pp. 65-76, 2009.
|
||||||
|
|
||||||
|
[2] RISC-V International, "The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA," Document Version 20211203, Dec. 2021.
|
||||||
|
|
||||||
|
[3] RISC-V International, "The RISC-V Instruction Set Manual, Volume II: Privileged Architecture," Document Version 20211203, Dec. 2021.
|
||||||
|
|
||||||
|
[4] JEDEC Solid State Technology Association, "JESD238: High Bandwidth Memory (HBM3) Standard," 2022.
|
||||||
|
|||||||
+15
-5
@@ -6,7 +6,7 @@
|
|||||||
# Providers
|
# Providers
|
||||||
# ------------------------------------------------------------
|
# ------------------------------------------------------------
|
||||||
|
|
||||||
PROVIDERS="openrouter ollama"
|
PROVIDERS="openrouter ollama qwen"
|
||||||
|
|
||||||
|
|
||||||
# ============================================================
|
# ============================================================
|
||||||
@@ -28,18 +28,28 @@ PROVIDER_ollama_KEY_ENV=""
|
|||||||
OLLAMA_CONTEXT=16384
|
OLLAMA_CONTEXT=16384
|
||||||
|
|
||||||
|
|
||||||
|
# ============================================================
|
||||||
|
# QWEN / DASHSCOPE
|
||||||
|
# ============================================================
|
||||||
|
|
||||||
|
PROVIDER_QWEN_URL="https://dashscope-intl.aliyuncs.com/compatible-mode/v1"
|
||||||
|
PROVIDER_QWEN_KEY_ENV="QWEN_API_KEY"
|
||||||
|
|
||||||
|
# Pick the Qwen model you want.
|
||||||
|
QWEN_MODEL="qwen3.7-plus"
|
||||||
|
|
||||||
# ============================================================
|
# ============================================================
|
||||||
# Agent routing
|
# Agent routing
|
||||||
# ============================================================
|
# ============================================================
|
||||||
|
|
||||||
# Powerful cloud model for research.
|
# Powerful cloud model for research.
|
||||||
RESEARCH_PROVIDER="openrouter"
|
RESEARCH_PROVIDER="qwen"
|
||||||
RESEARCH_MODEL="minimax/minimax-m3:free"
|
RESEARCH_MODEL="qwen3.7-plus"
|
||||||
|
|
||||||
|
|
||||||
# Local M4 reviewer.
|
# Local M4 reviewer.
|
||||||
REVIEW_PROVIDER="ollama"
|
REVIEW_PROVIDER="qwen"
|
||||||
REVIEW_MODEL="gemma4:12b"
|
REVIEW_MODEL="deepseek-v4-pro"
|
||||||
|
|
||||||
|
|
||||||
# Powerful cloud model for revisions.
|
# Powerful cloud model for revisions.
|
||||||
|
|||||||
Reference in New Issue
Block a user