PASS: Completed Review #6 | research/05-memory/atomics.md

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+2026-08-26T17:47:16Z	research/05-memory/atomics.md	1	research	success
+2026-08-26T17:49:45Z	research/05-memory/atomics.md	1	review	PASS

research/.xh1/runs/20260826T174543Z/candidate.md

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+# Atomics
+
+## 1. Overview
+
+Atomic operations are fundamental to synchronization, lockless data structures, and concurrent memory management in multi-core systems. In the context of the XH-1, a custom 128-core RISC-V processor, atomics present significant microarchitectural challenges. While a 4-core or 8-core system can tolerate cache-line ping-ponging and moderate interconnect traffic, a 128-core system amplifies contention, false sharing, and network saturation by orders of magnitude. 
+
+This document details the architectural requirements, implementation strategies, scalability bottlenecks, and cross-subsystem interactions for atomic operations in the XH-1 processor.
+
+## 2. RISC-V Architectural Requirements
+
+The XH-1 must comply with the RISC-V Atomic specification. Historically defined as the standard 'A' extension, the RISC-V ISA has recently modularized these features into two distinct extensions for finer granularity:
+
+1.  **Zaamo (Atomic Memory Operations)**: Defines the AMO (Atomic Memory Operation) instructions (e.g., `amoadd`, `amoswap`, `amoand`). These are read-modify-write operations that execute atomically with respect to other memory operations to the same address.
+2.  **Zalrsc (Load-Reserved/Store-Conditional)**: Defines the `lr` (Load-Reserved) and `sc` (Store-Conditional) instructions, which together provide a mechanism for atomic read-modify-write sequences.
+
+### Memory Ordering and RVWMO
+Atomics in RISC-V operate within the **RVWMO** (RISC-V Weak Memory Ordering) memory model. 
+*   **Acquire and Release Semantics**: AMO and `sc` instructions support `.aq` (acquire) and `.rl` (release) bits. These enforce Preserved Program Order (PPO) rules, ensuring that subsequent memory operations do not reorder before an acquire, and preceding operations do not reorder after a release.
+*   **Sequential Consistency**: An AMO or `sc` instruction with both `.aq` and `.rl` set provides sequentially consistent ordering for that specific memory location.
+
+### Reservation Semantics (Zalrsc)
+The RISC-V specification mandates strict rules for `lr`/`sc` reservations:
+*   A successful `lr` establishes a reservation set (typically a cache line).
+*   An `sc` will fail (return non-zero) if any other hart successfully stores to the reservation set between the `lr` and `sc`.
+*   **Mandatory Invalidation**: The architecture *requires* that a reservation be invalidated upon a context switch, or if the hart takes an interrupt or exception. 
+*   **Spurious Failures**: The architecture *permits* `sc` to fail spuriously, even if no other hart wrote to the address, though excessive spurious failures degrade performance.
+
+## 3. Implementation Approaches and Alternatives
+
+Implementing atomics efficiently requires deciding *where* the atomic operation is physically executed within the memory hierarchy.
+
+### Approach A: Core-Side Execution (L1 Cache)
+The AMO or `sc` is executed in the core's execution pipeline, interacting directly with the L1 data cache.
+*   **Mechanism**: The core requests exclusive ownership of the cache line. The ALU performs the read-modify-write locally. The modified line is written back.
+*   **Advantages**: Low latency for uncontended cases; simple pipeline integration.
+*   **Disadvantages**: Generates massive invalidation traffic. In a 128-core system, if multiple cores attempt an AMO on the same address, the cache line will ping-pong across the L1 caches, saturating the interconnect.
+
+### Approach B: Mid-Level Cache Execution (L2/L3)
+The AMO is forwarded to a shared L2 or private L3 slice.
+*   **Mechanism**: The L1 forwards the AMO request to the L3. The L3 controller performs the read-modify-write and returns the result.
+*   **Advantages**: Reduces L1 invalidation traffic; keeps the cache line resident in the shared cache.
+*   **Disadvantages**: Higher latency than L1 execution; requires complex state machines in the L3 controller to handle partial writes and data type conversions.
+
+### Approach C: Directory/Home Node Execution
+The AMO is routed to the directory controller or the "home node" responsible for the physical address.
+*   **Mechanism**: The interconnect routes the AMO directly to the memory controller or directory node. The operation is performed in the directory's scratchpad or the main memory interface.
+*   **Advantages**: Eliminates cache-line bouncing entirely. Highly scalable for 128 cores.
+*   **Disadvantages**: Highest latency for uncontended accesses; requires the directory protocol to natively support AMO payloads.
+
+## 4. Scalability Challenges in a 128-Core Architecture
+
+Scaling atomics from a few cores to 128 cores introduces severe non-linear performance degradation if not carefully managed.
+
+### 4.1. Contention and Interconnect Saturation
+Consider a highly contended 64-byte cache line (e.g., a global spinlock or a shared counter). 
+*   **Quantitative Impact**: In an 8x16 mesh interconnect, the maximum hop count is 22. Assuming 1 ns per hop, the network round-trip time (RTT) is ~44 ns. If AMOs are executed at the L1 (Approach A), every AMO requires acquiring exclusive ownership, invalidating the line in up to 127 other L1 caches. The invalidation/acknowledgment traffic for a single AMO could take >100 ns. 
+*   **Throughput Collapse**: Serialized execution at the home node limits throughput to $1 / (44\text{ns} + \text{memory latency}) \approx 10\text{M}$ ops/sec. If L1 ping-ponging occurs, effective throughput could drop below $2\text{M}$ ops/sec, leaving 126 cores idle.
+
+### 4.2. LR/SC Livelock
+In a 128-core system, the probability of `sc` failure increases drastically due to high contention and interrupt rates.
+*   If 128 harts attempt a compare-and-swap (CAS) loop using `lr`/`sc` on the same address, the probability of a successful `sc` for any given hart approaches $1/128$. 
+*   Furthermore, if the OS uses timer interrupts frequently, the mandatory reservation clearing on interrupt entry will cause `sc` to fail even in the absence of memory contention, leading to livelock.
+
+### 4.3. False Sharing
+With 128 cores, the likelihood of independent variables sharing a 64-byte cache line is high. An atomic update to one variable will invalidate the cache line for all other variables in the same block, causing unnecessary coherence traffic and stalling unrelated cores.
+
+## 5. Architectural Interactions
+
+### 5.1. Pipeline
+*   **Execution Unit**: AMOs require a dedicated read-modify-write execution unit or multiplexing of the existing ALU. 
+*   **Stalls**: An `sc` failure must be handled without architectural exception. The pipeline must squash the `sc` and allow the core to retry. AMOs with `.aq`/`.rl` bits may block subsequent memory operations, requiring the pipeline to track memory ordering buffers (MOBs) or store queues carefully.
+
+### 5.2. Cache Hierarchy and Coherence
+*   **State Transitions**: An AMO requires the cache line to transition to the Modified (M) or Exclusive (E) state in the MESI/MOESI protocol. 
+*   **Directory Protocol**: The coherence directory must process AMO requests. If an AMO arrives for a line in the Shared (S) state, the directory must issue invalidations to all sharing cores before granting the AMO, or perform the AMO locally if the protocol supports "Shared-Modify" transitions.
+
+### 5.3. Memory System and Interconnect
+*   **Payload Size**: The interconnect must support the payload size of AMOs (up to 64 bits for `amoadd.d`, or 128 bits if the Zicbom/Zve extensions are considered, though standard Zaamo is up to 64-bit). 
+*   **Ordering**: The interconnect must preserve the ordering of AMO requests to the same address to prevent race conditions at the home node.
+
+### 5.4. Interrupts and Exceptions
+*   **Reservation Clearing**: The hart's local reservation register must be cleared synchronously upon taking an interrupt, exception, or executing an `xret` (return from trap). 
+*   **Implementation**: This requires a hardware signal from the trap handler to the load/store unit to invalidate the `lr` state.
+
+### 5.5. Operating System
+*   **Futexes and Spinlocks**: The Linux kernel relies heavily on `lr`/`sc` for `cmpxchg` and futex operations. The OS expects `sc` to fail only under contention. Excessive spurious failures will cause the OS scheduler to consume excessive CPU cycles in retry loops.
+*   **Context Switching**: The OS does not need to save/restore the `lr` reservation state across context switches, as the architecture mandates its invalidation.
+
+### 5.6. Verification
+*   **RVWMO Compliance**: Verifying RVWMO with atomics is notoriously difficult. The XH-1 verification environment must utilize formal verification tools (e.g., RISC-V Formal Verification SIG tools) and execute extensive litmus tests (e.g., `mp`, `iriw`, `sb` with atomic variants) to ensure `.aq` and `.rl` bits correctly constrain memory reordering.
+
+### 5.7. Performance
+*   **IPC Impact**: Uncontended atomics should ideally execute in 1-2 cycles in the pipeline. Contended atomics will stall the pipeline. The performance monitor (PMU) must include events to track `sc` failures, AMO latency, and cache-line bouncing to allow software profiling.
+
+## 6. Unresolved Design Questions
+
+1.  **AMO Execution Location**: Should XH-1 execute AMOs in the L1 cache (lower latency, high traffic) or at the L3/Home node (higher latency, high scalability)? *See Section 7 for proposal.*
+2.  **LR/SC Livelock Mitigation**: Should the microarchitecture implement hardware-level backoff or priority mechanisms for `sc` retries, or should this be left entirely to software (compiler/OS)?
+3.  **Reservation Set Granularity**: The RISC-V spec allows the reservation set to be larger than the requested address. Should XH-1 strictly limit the reservation set to the exact 64-byte cache line, or allow it to cover a larger physical page to simplify hardware?
+4.  **Zaamo/Zalrsc Modularity**: Will XH-1 implement both Zaamo and Zalrsc, or only one? (Linux requires both for standard operation).
+
+## 7. Proposals and Recommendations
+
+Based on the scalability requirements of a 128-core architecture, the following proposals are submitted for the XH-1 design:
+
+### Proposal 1: Home-Node AMO Execution
+**XH-1 Proposal**: Execute all Zaamo (AMO) instructions at the directory home node (or L3 slice acting as the home node) rather than in the L1 cache.
+*   **Rationale**: In a 128-core system, L1-based AMOs will cause catastrophic invalidation storms. By routing AMOs to the home node, the cache line remains in the shared L3, and only the directory state is updated. This trades a small amount of uncontended latency (approx. 20-30 ns) for massive gains in contended throughput and interconnect bandwidth preservation.
+
+### Proposal 2: Strict Cache-Line Reservation Tracking
+**XH-1 Proposal**: Implement `lr`/`sc` reservations strictly at the 64-byte cache line granularity.
+*   **Rationale**: While the RISC-V spec permits larger reservation sets, a larger set (e.g., page-level) would cause `sc` to fail spuriously when unrelated data in the same page is modified by other cores. In a 128-core system, page-level reservations would render `lr`/`sc` practically unusable due to constant spurious failures.
+
+### Proposal 3: Hardware-Assisted LR/SC Backoff (Under Investigation)
+**XH-1 Proposal**: Investigate the addition of a microarchitectural, hardware-assisted exponential backoff for `sc` instructions.
+*   **Rationale**: To prevent livelock and interconnect saturation when multiple harts spin on the same `lr`/`sc` loop, the load/store unit could introduce a small, randomized stall before allowing the `sc` to attempt the store. *Note: This must be carefully designed to ensure it does not violate the architectural visibility of memory operations or introduce deadlocks.*
+
+### Recommendation: PMU Extensions for Atomics
+It is strongly recommended to include specific Performance Monitoring Unit (PMU) counters for:
+*   `sc` instruction failures (distinguishing between contention-induced and spurious/interrupt-induced if possible).
+*   AMO execution latency.
+*   Cache line invalidations triggered specifically by atomic operations.
+These counters are critical for OS developers and application programmers to optimize lockless algorithms on a 128-core system.

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+research/05-memory/atomics.md

research/.xh1/runs/20260826T174543Z/review.md

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+**Review of research/05-memory/atomics.md**
+
+The document provides a clear and structured discussion of atomic operations in the context of a 128‑core RISC‑V processor. It correctly identifies the key scalability challenges, reviews several implementation approaches, and outlines reasonable proposals for the XH‑1 design. The overall technical intent is sound, and the document is appropriate for its research stage.
+
+However, a few issues must be addressed before acceptance, and several minor points deserve attention.
+
+**1. Factual / Specification Error (must fix)**
+- In Section 5.3, the claim that AMO payload sizes could be 128 bits “if the Zicbom/Zve extensions are considered” is incorrect. Zicbom is a cache‑block‑management extension, and Zve is the vector extension; neither introduces 128‑bit atomic memory operations. The standard `Zaamo` extension defines only 8‑, 16‑, 32‑, and 64‑bit AMOs. The erroneous reference to Zicbom/Zve creates a misunderstanding of the ISA and should be removed.
+
+**2. Unsupported Performance Claims**
+- The document estimates that L1‑based AMO ping‑ponging could reduce throughput to “below 2 M ops/sec” and that in an LR/SC loop the probability of success for a given hart “approaches 1/128.” These are rough, unsupported estimates presented without simulation data, analytical modeling, or references. While they are illustrative, they are stated as if they are quantitative conclusions. They should either be removed or explicitly labelled as speculative order‑of‑magnitude guesses.
+
+**3. Reservation Invalidation on `xret`**
+- Section 5.4 states that the reservation register “must be cleared … upon executing an `xret`.” The RISC‑V specification requires clearing on a context switch, interrupt, or exception, but does not explicitly require clearing on `xret`. In practice the reservation is already lost because the trap entry cleared it; the statement is therefore slightly misleading. It is not a serious error, but it would be better to clarify that the reservation is **already** invalidated by the time `xret` executes.
+
+**4. Missing Discussion of Power/Area Implications**
+- The review criteria include power and area considerations. The document does not address the power or area cost of the proposed AMO execution location (home‑node vs. L1), the hardware‑assisted backoff, or the additional PMU counters. For a complete research document, a brief mention of these trade‑offs would be expected.
+
+**5. Lack of Supporting Citations**
+- The document contains no references to the RISC‑V specification, existing literature on atomics scaling, or prior work on directory‑based AMO execution. While not mandatory for an internal research note, the absence of any citations weakens the evidence base for the proposals.
+
+**Verdict**
+
+Despite these points, the document is technically credible for its research stage. The necessary fix is minor and straightforward. The verdict is **PASS** with the required correction of the Zicbom/Zve error.
+
+```json
+{
+  "verdict": "PASS",
+  "confidence": "HIGH",
+  "issues": [
+    "The claim that the probability of a successful sc for a given hart approaches 1/128 is an unsupported approximation.",
+    "The estimate that L1‑based AMO throughput could drop below 2 M ops/sec is unsupported by any analysis or data.",
+    "The statement that the reservation must be cleared upon executing xret is slightly inaccurate; it is already cleared by the interrupting trap. The phrasing should be clarified.",
+    "The document does not discuss power or area implications of the proposed AMO execution strategies.",
+    "No citations are provided to support the claimed scalability limits or to reference the RISC‑V specification."
+  ],
+  "required_fixes": [
+    "Remove the incorrect reference to Zicbom/Zve in Section 5.3. The standard Zaamo extension supports only up to 64‑bit AMO payloads; there is no 128‑bit AMO in Zicbom or Zve. Correct the sentence to state that the interconnect must support payloads up to 64 bits (or 8/16/32/64 bits) for AMO instructions."
+  ]
+}
+```