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This document is an early-stage engineering research artifact. Many quantitative claims below are estimates pending empirical validation against synthesized netlists, layout, and workload characterization.\n\n## Abstract\n\nThe multiply-divide (MUL/DIV) unit implements the integer multiplication and division instructions defined in the RV64IM (and optionally M-extension) instruction set. In XH-1, the MUL/DIV unit sits on the execution path of each of the 128 cores, and its latency, throughput, area, and energy directly influence per-core performance and the die-level power/thermal envelope. This document surveys existing MUL/DIV architectures (iterative, array, Radix-4/8 Booth, array-of-serial, and Sutherland/Robertson division), compares their trade-offs, and proposes a design direction suitable for a 128-core RISC-V processor where replication, area, and energy are first-class constraints.\n\n## Research Question\n\nWhat MUL/DIV architecture best fits XH-1's 128-core RISC-V design, given:\n\n- Per-core area must be small enough to replicate 128 instances on one die.\n- The pipeline stage budget for the EX stage is finite (TBD by `pipeline.md`).\n- The unit is on a non-critical path for most general-purpose code but is on the critical path for scientific, cryptographic, hash, and DSP workloads.\n- The unit should be IEEE 754-friendly if floating-point support is integrated later, but for this document the scope is integer MUL/DIV.\n- Verification must scale to 128 cores; deterministic, fully combinational MUL and bounded-iteration DIV designs simplify verification.\n\n## Background\n\n### Required Instructions (RV64M)\n\nThe Rv64M extension defines:\n- MUL, MULH, MULHSU, MULHU (64x64 -> 128-bit multiply).\n- DIV, DIVU, REM, REMU (64-bit signed/unsigned divide and remainder).\n- MULW, DIVW, DIVUW, REMW, REMUW (32-bit signed/unsigned, sign-extended to 64 bits).\n\n### Latency Requirements (typical)\n\nOpenRISC, Rocket, BOOM, and commercial cores report the following typical latencies (estimates, to be validated against target frequency):\n\n| Operation        | Typical latency (cycles) | Throughput      |\n|------------------|--------------------------|-----------------|\n| MUL (lower 64)   | 3–5                      | 1/cycle or pipelined |\n| MULH (upper 64)  | 4–6                      | 1/cycle or pipelined |\n| DIV/REM (64-bit) | 20–40                    | 1 per 20–40 cycles |\n| MULW/DIVW        | similar to 64-bit        | similar         |\n\nThese numbers vary widely with frequency, area, and architecture; the repository does not yet contain measurements.\n\n### Division Algorithms (Background)\n\n- Restoring division: simple, but slow (one bit per cycle).\n- Non-restoring division: similar latency, less area than array.\n- SRT division (e.g., radix-2, radix-4): higher radix = fewer iterations, more complex quotient-digit selection logic.\n- Newton-Raphson reciprocal multiplication: pre-computes reciprocal via iteration, then multiplies. Fastest for many workloads, but variable latency, complex control.\n- Goldschmidt division: similar trade-off to Newton-Raphson.\n\n### Multiplication Algorithms (Background)\n\n- Shift-and-add multiplier: simple, slow.\n- Array (Braun/baugh-wooley) multiplier: combinational, O(n²) area, deterministic latency.\n- Wallace/Dadda tree multiplier: O(n log n) partial-product reduction, faster, more irregular layout.\n- Booth-encoded multipliers (radix-4, radix-8): reduce partial-product count by 2× or 3×.\n- Compressor-tree (3:2, 4:2) approaches.\n\n## Existing Approaches\n\n### A1. Iterative Shift-and-Add Multiplier + Restoring Divider\n\n- Implementation: one 64-bit adder, 130-bit accumulator, shift register.\n- Multiplier: 64 cycles, 1 bit/cycle.\n- Divider: 64 cycles (restoring) or ~64 cycles (non-restoring).\n- Area: very small.\n- PROPOSAL-class baseline for comparison only.\n\n### A2. Booth-Radix-4 Multiplier + Iterative Divider\n\n- Multiplier: 32 partial products, Wallace/Dadda reduction, 2-stage pipelined, 2-cycle latency, 1/cycle throughput.\n- Divider: 64-cycle non-restoring.\n- Area: small-to-medium.\n- Used in many embedded RV cores (e.g., SiFive E-class predecessors).\n\n### A3. Pipelined Radix-4/8 Booth + Radix-4 SRT Divider\n\n- Multiplier: 2–3 stage pipeline, 1/cycle issue, latency 2–3 cycles.\n- Divider: radix-4 SRT, ~16 cycles, ~1 per 16 cycles throughput.\n- Area: medium.\n- Used in superscalar cores (e.g., BOOM-family, Ariane-derived).\n\n### A4. Fully Combinational Array Multiplier + Radix-16 SRT Divider\n\n- Multiplier: 64×64 → 128, single cycle, large area.\n- Divider: 4–8 cycles, 1 per 4–8 cycles throughput.\n- Area: large.\n- Used in high-frequency superscalar out-of-order cores.\n\n### A5. Shared/Vector MUL-DIV Unit (per-cluster)\n\n- A single MUL/DIV unit is shared across N cores, accessed via a reservation station.\n- Saves replicated area; increases latency and contention.\n- Used in some throughput-oriented many-core designs.\n\n## Alternative Designs\n\n### B1. 2-Stage Pipelined Radix-4 Booth Multiplier\n\n- 17 partial products reduced via 4:2 compressor tree.\n- Two pipeline stages: partial-product reduction, then final carry-propagate add.\n- Latency 2 cycles, throughput 1/cycle.\n- Divider: 32-cycle non-restoring (radix-2 non-restoring with early-exit optimization).\n\n### B2. 3-Stage Pipelined Radix-8 Booth Multiplier\n\n- 11 partial products.\n- Latency 3 cycles, throughput 1/cycle.\n- Smaller critical path than B1, higher area.\n\n### B3. Iterative Multiplier with Multi-Cycle Variable Latency\n\n- Single 64×64 multiplier reused across MUL/MULH/MULHU by selecting the relevant output bits.\n- Latency 4–5 cycles, 1/cycle throughput.\n- Smaller area than B1 but longer latency.\n\n### B4. Radix-4 SRT Divider with Pipelined Issue\n\n- 16-cycle latency, fully pipelined so back-to-back divides (with different operands) are allowed.\n- Larger area, more verification complexity.\n\n### B5. Newton-Raphson Divider with Hardware Reciprocal Iteration\n\n- ~4–6 cycles for 32-bit reciprocal, then 1 multiply.\n- Lowest divide latency, but variable and dependent on operand class.\n- Complex verification (convergence proofs required).\n\n### B6. Two's-Complement Array Divider (Combinational)\n\n- Single-cycle 64-bit divide.\n- Extremely large area (~64× of a 64-bit multiplier).\n- Likely unacceptable for 128-core replication.\n\n## Comparison\n\n| Design | MUL Latency | MUL Throughput | DIV Latency | DIV Throughput | Relative Area | Verification Complexity |\n|--------|-------------|----------------|-------------|----------------|---------------|-------------------------|\n| A1. Shift-add + restoring | 64 | 1/64 | 64 | 1/64 | 1× | Low |\n| A2. Booth-r4 + NR div    | 2  | 1/1   | 32 | 1/32 | ~3–4× | Low–Medium |\n| A3. Pipelined r4/r8 + SRT-4 | 2–3 | 1/1 | 16 | 1/16 | ~5–7× | Medium |\n| A4. Combinational + SRT-16  | 1  | 1/1 | 4–8 | 1/8  | ~10–15× | High |\n| B1. 2-stage r4 + NR-32    | 2  | 1/1   | 32 | 1/32 | ~3–5× | Low–Medium |\n| B4. Pipelined SRT-4        | n/a | n/a | 16 | 1/16 | adds ~3–4× | Medium |\n| B5. Newton-Raphson        | 1 (MUL) | 1/1 | 4–6 | 1/4–6 | ~6–8× | High |\n| B6. Combinational array   | 1  | 1/1   | 1  | 1/1  | ~50× | Medium |\n\nPROPOSAL: A representative B1+B4 hybrid is a 2-stage pipelined Radix-4 Booth multiplier paired with a pipelined Radix-4 SRT divider. This is a reasonable starting point pending synthesis-driven PPA feedback.\n\n## Advantages\n\n- A 2-stage pipelined Radix-4 Booth multiplier offers 1/cycle throughput at modest area, suitable for a replicated 128-core design.\n- A pipelined Radix-4 SRT divider (or a non-restoring iterative divider with early-exit) meets the latency needs of most workloads without dominating area.\n- Deterministic latencies (vs. Newton-Raphson) simplify pipeline scheduling, forwarding, and verification.\n- Radix-4 Booth and SRT-4 are well-understood and have reference implementations in academic and open-source RISC-V cores.\n\n## Disadvantages\n\n- 16-cycle SRT-4 divide is still slow for workloads dominated by large-integer arithmetic (RSA, big-integer math).\n- Combinational or Newton-Raphson dividers reduce latency significantly but at unacceptable area/verification cost for 128-core replication.\n- A non-restoring iterative divider has the lowest area but penalizes every divide by ~32 cycles, which can be felt in hash-table probing, parser/lexer dispatch, and some interpreters.\n- Booth encoding complicates verification of signed/unsigned correctness (MULH vs. MULHSU vs. MULHU).\n\n## XH-1 Considerations\n\n- ASSUMPTION: XH-1 is a 128-core design with a relatively short pipeline (TBD by `pipeline.md`). The MUL/DIV unit must fit in a small per-core area budget and the EX stage latency budget.\n- ASSUMPTION: The design targets a balance of general-purpose and HPC-adjacent workloads; therefore a moderately fast (but not the fastest) divider is acceptable.\n- PROPOSAL: Adopt a 2-stage pipelined Radix-4 Booth multiplier (MUL, MULH, MULHSU, MULHU, MULW) and a 32-cycle non-restoring iterative divider with early-exit optimization.\n- The multiplier is sized to produce the full 128-bit product so that MULH/MULHU selection requires only output muxing, not a separate datapath.\n- The W-variants (MULW, DIVW, etc.) reuse the lower 32 bits of the 64-bit datapath with sign-extension at the output.\n\n### Instruction Coverage\n\n- MUL/MULH/MULHSU/MULHU: supported.\n- DIV/DIVU/REM/REMU: supported, with corner cases (÷0, INT_MIN/-1, signed overflow per spec) handled explicitly.\n- MULW/DIVW/DIVUW/REMW/REMUW: supported via shared datapath.\n\n### Edge Cases\n\n- Division by zero: returns -1 for DIV, x for DIVU, per RISC-V spec; the unit must produce the architecturally specified result without exception.\n- Signed overflow (INT64_MIN / -1): returns INT64_MIN for DIV, 0 for REM.\n- These cases are common sources of bugs and require explicit test coverage.\n\n## 128-Core Scalability\n\n- Area: replicating 128 copies of even a moderately sized MUL/DIV unit is a significant die-level cost. The chosen design (B1+B4 baseline) is estimated at <1–2% of a typical small RV core area, but 128× replication is non-trivial.\n- Floorplanning: a regular MUL/DIV layout that mirrors across cores is preferred to avoid routing asymmetry that would break clock distribution.\n- Voltage/Frequency: a deeply pipelined MUL/DIV is more resilient to voltage droop; this is an advantage for 128-core operation.\n- Contention: there is no inter-core contention for the MUL/DIV unit (per-core replication); the only contention is intra-core (two dependent divides in flight).\n- Test/DFT: 128 instances of the MUL/DIV unit must be tested; a scan-friendly, fully synchronous design with no asynchronous reset paths inside the iterative divider is preferable.\n\n## Performance Considerations\n\n- For general-purpose code, MUL/DIV is rarely the bottleneck; the chosen 2-cycle MUL latency matches typical issue-to-use distances.\n- For cryptography (AES SubBytes via GF(2⁸), polynomial multiplies, RSA), MUL throughput is the key metric — 1/cycle is the floor for acceptable performance.\n- For hash tables and interpreters, DIV latency matters more than throughput; a 32-cycle divider is acceptable but not ideal.\n- For 64-bit polynomial multiplication, MULH throughput is the key metric.\n- For 32-bit integer code, the W-variants are the hot path; reusing the 64-bit datapath with muxed operands is acceptable.\n\n## Area Considerations\n\n- ASSUMPTION: A 64×64 → 128-bit Radix-4 Booth multiplier with a 4:2 compressor tree and 2-stage pipelined final adder occupies roughly 0.05–0.10 mm² in a typical 7nm process.\n- ASSUMPTION: A 32-cycle non-restoring iterative divider occupies roughly 0.02–0.05 mm².\n- PROPOSAL: Total MUL/DIV area target: <0.15 mm² per core. 128× replication: ~20 mm². INSUFFICIENT EVIDENCE to refine this without a technology file.\n- The 4:2 compressor tree is more area-efficient than a Wallace tree for radix-4.\n- Sign-extension and zero-extension muxes for MULW are negligible area.\n\n## Power and Energy Considerations\n\n- A 64×64 multiplier tree has high switching activity; clock gating when the unit is idle is essential.\n- The iterative divider has lower average power than a fully combinational divider, but its long residency increases leakage energy per operation.\n- Power gating: at 128 cores, a per-core power-gate for the MUL/DIV unit is worth considering if idle periods dominate.\n- Energy per multiply: dominated by the compressor tree; energy scales roughly with the number of partial products.\n- Energy per divide: dominated by the 32-cycle residency; techniques to short-circuit trailing zeros in the dividend (early-exit) can reduce energy in common cases.\n\n## Implementation Considerations\n\n- Use synchronous, single-clock-domain design inside the unit.\n- Avoid asynchronous resets inside the iterative divider; use synchronous reset only at the start of an operation.\n- Multiplier carry-propagate adder should be a Kogge-Stone or Han-Carlson adder for speed, with a Brent-Kung fallback if area is tight.\n- Divider quotient/remainder registers are 64 bits each, with an extra bit for the iterative sign.\n- Microarchitectural state machine is small and well-suited to a one-hot or binary-encoded FSM.\n- Output muxing for MUL/MULH/MULHSU/MULHU/MULW is a small mux tree, not a separate datapath.\n- Booth encoding produces 33 partial products for radix-4 of a 64-bit operand; reduction to 2 operands via compressor tree.\n\n## Verification Considerations\n\n- Formal verification of the multiplier compressor tree + final adder is feasible with bounded model checkers and is recommended.\n- Directed tests for division edge cases (÷0, INT_MIN/-1, dividend=d divisor=1, dividend=0 divisor=x, all-ones, alternating bits).\n- Randomized differential testing against a software reference (e.g., a GCC-compiled test harness running on Spike or QEMU) is recommended.\n- Coverage of all 4 MUL variants and 4 MULH variants plus the W-variants.\n- 128-core DFT: scan stitching should be reviewed to ensure no long scan chains between the iterative divider and surrounding logic cause hold-time issues.\n- Reference models: a Python or C++ golden model for the entire RV64M ISA is recommended and reusable across all 128 cores.\n- UVM or cocotb-based testbenches: the unit is small enough that a single high-quality testbench can be reused.\n\n## Software Implications\n\n- Compilers will emit MUL freely; no software changes are required.\n- Division by a constant is often transformed by the compiler into a magic-number multiply; the choice of MUL/DIV design therefore disproportionately affects runtime divide performance.\n- For languages with software-emulated 128-bit integers (e.g., __int128 in C/C++), the compiler will emit MULH/MULHU sequences; MULH latency and throughput become important.\n- Crypto libraries (libsodium, OpenSSL, mbedTLS) often use Karatsuba or Montgomery multiplication, which benefit from 1/cycle MULH throughput.\n- JavaScript engines and language runtimes may issue frequent DIVs for tagged-value unpacking; a slow divider increases interpreter overhead.\n\n## Recommendation\n\nPROPOSAL: Adopt a 2-stage pipelined Radix-4 Booth multiplier paired with a 32-cycle non-restoring iterative divider (with early-exit optimization for the dividend). Provide pipelined throughput of 1 MUL per cycle and 1 DIV per 32 cycles.\n\nRationale:\n- Best balance of area, energy, and performance for 128-core replication.\n- Deterministic, fully synchronous design simplifies verification and DFT.\n- 1/cycle MUL throughput meets crypto and HPC-adjacent needs.\n- 32-cycle DIV latency is acceptable for general-purpose workloads; can be revisited if profiling shows a hotspot.\n\nRECOMMENDATION (with caveats): If early workload analysis (TBD) shows that divide latency is a bottleneck, consider upgrading the divider to a pipelined Radix-4 SRT (16 cycles) at ~3–4× the divider area. Do not adopt a Newton-Raphson divider unless profiling evidence strongly supports it, due to verification complexity.\n\nRECOMMENDATION: Do not adopt a fully combinational array divider or fully combinational multiplier for the replicated 128-core design. The area cost is not justified by the latency benefit.\n\n## Confidence\n\n- Direction of recommendation: MEDIUM. The general design class is well-established; specific numbers (area, latency, energy) require synthesis runs against a target technology library.\n- Quantitative area/power numbers: LOW. No measurements exist in the repository; all such numbers in this document are estimates.\n- Verification strategy: HIGH. The recommended approach (formal on the multiplier, directed + randomized for the divider) is standard practice.\n- Edge-case correctness: HIGH. The RISC-V spec is explicit and well-tested across many cores.\n\n## Open Questions\n\n- What is the EX-stage latency budget? (Depends on `pipeline.md`.)\n- What is the target frequency and process node? Determines whether 1-cycle or 2-cycle MUL is feasible.\n- Is the design in-order or out-of-order? Out-of-order execution can hide divide latency; in-order cannot.\n- Will the MUL/DIV unit share an issue port with the ALU, or have a dedicated issue port? (Likely shared, but TBD.)\n- Is there a future F/D extension? If so, the integer MUL/DIV unit may also need to handle FP-to-int conversions or FP reciprocal iterations.\n- What is the workload mix expected? Scientific (HPC) vs. general-purpose vs. embedded?\n- Should the MUL/DIV unit be power-gated when idle? At 128 cores, idle probability may be high.\n- Should the divider support a \"fast-path\" for division by a small constant (e.g., compiler-inserted reciprocal multiply hint)?\n\n## Sources\n\n- The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA — defines M-extension semantics. (Documented in standard ISA references; no specific URL is cited here per the no-fabrication rule.)\n- Hennessy and Patterson, \"Computer Architecture: A Quantitative Approach\" — covers MUL/DIV trade-offs.\n- Parhami, \"Computer Arithmetic: Algorithms and Hardware Designs\" — covers multiplier and divider algorithms in depth.\n- Open-source RISC-V cores (e.g., Rocket, BOOM, Ariane) for design-class references. Specific measurements, layouts, and PPA numbers: INSUFFICIENT EVIDENCE in the current XH-1 repository.\n- No quantitative claims in this document are derived from measurements; all are estimates unless explicitly labeled otherwise.","refusal":null,"reasoning":null}}],"usage":{"prompt_tokens":706,"completion_tokens":4528,"total_tokens":5234,"cost":0,"is_byok":false,"prompt_tokens_details":{"cached_tokens":691,"cache_write_tokens":0,"audio_tokens":0,"video_tokens":0},"cost_details":{"upstream_inference_cost":0,"upstream_inference_prompt_cost":0,"upstream_inference_completions_cost":0},"completion_tokens_details":{"reasoning_tokens":0,"image_tokens":0,"audio_tokens":0}}}