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Substantive research has not yet been written.\n\n## Abstract\nINSUFFICIENT EVIDENCE. The current document contains no technical content. This section will summarize the chosen per-core verification methodology (simulation-based, formal, FPGA prototyping, or hybrid), the coverage targets, and the relationship to the broader 10-verification strategy once defined.\n\n## Research Question\nThe specific research question for this document is not yet formulated. Candidate questions include:\n- What is the minimum set of per-core verification techniques required to achieve a stated sign-off confidence target for a single XH-1 core before replication to 128 instances?\n- How should directed, constrained-random, and formal methods be partitioned across the core's microarchitectural units (fetch, decode, rename, issue, execute, memory, retire, CSR, MMU, PMP, debug, trace)?\n- What coverage model (line, branch, toggle, functional, assertion, mutation) is required at the core level versus deferred to multicore verification?\n\n## Background\nINSUFFICIENT EVIDENCE. No prior XH-1 core-verification decisions are recorded. Industry baseline: core-level verification of modern RISC-V cores (e.g., SiFive, Andes, OpenHW Group CV32E40P/E40PX) typically combines constrained-random simulation with a defined coverage model, supplemented by formal property checks on targeted blocks (e.g., CSR file, MMU TLB, scoreboard/ROB). The RISC-V ISA provides architectural compliance tests (riscv-tests) that form a baseline but are not sufficient on their own.\n\n## Existing Approaches\nINSUFFICIENT EVIDENCE to compare specific commercial EDA or academic flows without repository context. General categories that exist in the field:\n- Constrained-random UVM/SystemVerilog simulation with coverage-driven closure\n- Formal property verification (JasperGold, Cadence Jasper, Synopsys Formality/VC-Formal, Onespin, RVX) on selected sub-modules\n- FPGA prototyping/emulation acceleration\n- Co-simulation with architectural reference models (e.g., Spike, SAIL, riscvOVPsim)\n- Compliance test suites: riscv-tests, riscv-arch-test, RISC-V International signing framework\n- Mutation-based verification tools\n- Coverage merging across simulators/prototypes\n\n## Alternative Designs\nINSUFFICIENT EVIDENCE. The repository has not yet selected between approaches such as:\n- Pure simulation-driven sign-off vs. hybrid simulation + formal\n- In-house UVM testbench vs. commercial VIP vs. generator-based (e.g., riscv-dv from Google/CHIPS Alliance) flows\n- Single-language (SystemVerilog) vs. multi-language (SystemVerilog + Cocotb/Chisel/SpinalFlow co-simulation) environments\n- Coverage model: line/branch/toggle only vs. full functional coverage matrix indexed by ISA extension × privilege level × interrupt/exception path\n\n## Comparison\nINSUFFICIENT EVIDENCE. Quantitative trade-offs (run time, license cost, engineering effort, coverage closure time, debug productivity) cannot be cited without source data.\n\n## Advantages\nINSUFFICIENT EVIDENCE. The document does not yet commit to a methodology, so advantages of any chosen approach cannot be stated.\n\n## Disadvantages\nINSUFFICIENT EVIDENCE.\n\n## XH-1 Considerations\nASSUMPTION: because XH-1 is a custom 128-core RISC-V design, core-level verification must produce a sign-off artifact that is reusable across all 128 replicated instances. Open questions that bear on this:\n- Whether the 128 cores are identical (homogeneous) or partially heterogeneous (e.g., different privileged/IoT variants). The current document does not state this.\n- Whether per-core verification is gated on the L1 cache, MMU/TLB, and coherence-related agent behavior, or whether those are deferred to the multicore verification document. That boundary is not defined.\n- How the debug (RISC-V Debug Spec 0.13/1.0) and trace (RISC-V Trace Spec) modules are partitioned.\n\n## 128-Core Scalability\nPROPOSAL: structure core-level sign-off so that verification collateral (testbench, sequences, assertions, coverage models) is parameterizable by core index / instance ID, allowing reuse when validating replicated cores. This avoids redeveloping verification for each of the 128 instances.\n\nASSUMPTION: the 128-core design reuses a single verified core RTL. If cores are unique, this scalability argument does not apply directly.\n\nOPEN QUESTION: does XH-1 use a tiled layout with replicated cores, a mesh/NoC of heterogeneous cores, or a mix? Not stated in the document or related research artifacts.\n\n## Performance Considerations\nINSUFFICIENT EVIDENCE. Core-level simulation throughput (instructions/sec, coverage points/hour) depends on the chosen simulator (commercial event-driven, open-source Verilator, cocotb, etc.) which is not yet selected in this document.\n\n## Area Considerations\nINSUFFICIENT EVIDENCE. Verification-influenced area decisions (e.g., adding observability/assertion logic, formal-friendly state encoding) have not been characterized.\n\n## Power and Energy Considerations\nINSUFFICIENT EVIDENCE.\n\n## Implementation Considerations\nASSUMPTION: the design captures the RISC-V ISA, the privilege levels, and the specific extensions (RV32I/RV64I, M, A, F/D, C, V, B, K, H, etc.) that the core must implement. None of this is captured in the current document set, all of which are stubs.\n\nASSUMPTION: a reference model (Spike, SAIL, or hand-written golden) will be available for differential checking.\n\n## Verification Considerations\nPROPOSAL: define a coverage closure plan with explicit exit criteria before any RTL is signed off. Candidates:\n- Functional coverage: every instruction in every supported extension × every privilege mode × representative operand values (0, 1, -1, max, NaN-boxed, sign-extension edge cases).\n- Exception/interrupt coverage: every exception cause × every priority × MRET/SRET/URET paths × nested traps.\n- CSR coverage: every CSR address × every writable bit × reset value × WARL semantics.\n- Memory access coverage: misaligned, PMP-denied, MMU miss, page-fault, atomics, fence ordering, I/O regions.\n- Reset and debug entry/exit: every reset reason (power-on, debug, warm, retention) and every debug state transition.\n- Formal: targeted unbounded proofs for FSMs, scoreboard/ROB, MMU TLB invariants, exception priority encoders.\n\nOPEN QUESTION: what is the coverage closure target (e.g., 100% legal-bin coverage, X% toggle, X% mutation score)? Not stated.\n\n## Software Considerations\nPROPOSAL: align core verification artifacts with downstream software flows:\n- The architectural compliance test signature (riscv-arch-test) must be producible from the verified core so that OS porters and toolchain builders can adopt the platform.\n- A linker script, boot ROM, and SBI interface contract should be specified in parallel with the core's CSRs to avoid post-silicon software surprises.\n- A pre-silicon architectural reference (Spike-compatible or SAIL) should be published for software teams.\n\n## Recommendation\nINSUFFICIENT EVIDENCE. The current document does not contain enough context (ISA profile, microarchitecture choice, EDA toolchain, sign-off criteria) to recommend a specific core-verification methodology. A recommendation is not forced.\n\n## Confidence\nLow. The document is a stub; no research has been performed.\n\n## Open Questions\n- What RISC-V base and extensions does XH-1 implement (RV32/RV64, I/M/A/F/D/C/V/B/H/K, privilege modes, hypervisor)?\n- Is the core in-order or out-of-order? This dramatically changes the verification surface (e.g., scoreboard, load-store queue, speculation recovery).\n- Is the 128-core array homogeneous, or are there variants (e.g., application cores + management/IoT cores)?\n- What simulator stack is available or mandated (commercial, Verilator, cocotb, custom)?\n- What is the targeted process node, clock frequency, and tape-out timeline? These bound verification wall-clock time.\n- Does the project have access to FPGA prototyping capacity at the scale required to boot 128 cores?\n- What is the project's stance on the RISC-V International compliance sign-off process?\n- Which verification sub-area (formal, fault injection, ISA compliance, multicore, regression, strategy, unit) should consume artifacts produced at the core level?\n- What coverage exit criteria does the project accept for tape-out?\n- How is debug and trace verification partitioned between this document and multicore verification?\n\n## Sources\nNo sources cited. The document contains no factual claims requiring attribution. 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