# Multiply-Divide Unit

## Status

Stub. This document is an early-stage engineering research artifact. Many quantitative claims below are estimates pending empirical validation against synthesized netlists, layout, and workload characterization.

## Abstract

The multiply-divide (MUL/DIV) unit implements the integer multiplication and division instructions defined in the RV64IM (and optionally M-extension) instruction set. In XH-1, the MUL/DIV unit sits on the execution path of each of the 128 cores, and its latency, throughput, area, and energy directly influence per-core performance and the die-level power/thermal envelope. This document surveys existing MUL/DIV architectures (iterative, array, Radix-4/8 Booth, array-of-serial, and Sutherland/Robertson division), compares their trade-offs, and proposes a design direction suitable for a 128-core RISC-V processor where replication, area, and energy are first-class constraints.

## Research Question

What MUL/DIV architecture best fits XH-1's 128-core RISC-V design, given:

- Per-core area must be small enough to replicate 128 instances on one die.
- The pipeline stage budget for the EX stage is finite (TBD by `pipeline.md`).
- The unit is on a non-critical path for most general-purpose code but is on the critical path for scientific, cryptographic, hash, and DSP workloads.
- The unit should be IEEE 754-friendly if floating-point support is integrated later, but for this document the scope is integer MUL/DIV.
- Verification must scale to 128 cores; deterministic, fully combinational MUL and bounded-iteration DIV designs simplify verification.

## Background

### Required Instructions (RV64M)

The Rv64M extension defines:
- MUL, MULH, MULHSU, MULHU (64x64 -> 128-bit multiply).
- DIV, DIVU, REM, REMU (64-bit signed/unsigned divide and remainder).
- MULW, DIVW, DIVUW, REMW, REMUW (32-bit signed/unsigned, sign-extended to 64 bits).

### Latency Requirements (typical)

OpenRISC, Rocket, BOOM, and commercial cores report the following typical latencies (estimates, to be validated against target frequency):

| Operation        | Typical latency (cycles) | Throughput      |
|------------------|--------------------------|-----------------|
| MUL (lower 64)   | 3–5                      | 1/cycle or pipelined |
| MULH (upper 64)  | 4–6                      | 1/cycle or pipelined |
| DIV/REM (64-bit) | 20–40                    | 1 per 20–40 cycles |
| MULW/DIVW        | similar to 64-bit        | similar         |

These numbers vary widely with frequency, area, and architecture; the repository does not yet contain measurements.

### Division Algorithms (Background)

- Restoring division: simple, but slow (one bit per cycle).
- Non-restoring division: similar latency, less area than array.
- SRT division (e.g., radix-2, radix-4): higher radix = fewer iterations, more complex quotient-digit selection logic.
- Newton-Raphson reciprocal multiplication: pre-computes reciprocal via iteration, then multiplies. Fastest for many workloads, but variable latency, complex control.
- Goldschmidt division: similar trade-off to Newton-Raphson.

### Multiplication Algorithms (Background)

- Shift-and-add multiplier: simple, slow.
- Array (Braun/baugh-wooley) multiplier: combinational, O(n²) area, deterministic latency.
- Wallace/Dadda tree multiplier: O(n log n) partial-product reduction, faster, more irregular layout.
- Booth-encoded multipliers (radix-4, radix-8): reduce partial-product count by 2× or 3×.
- Compressor-tree (3:2, 4:2) approaches.

## Existing Approaches

### A1. Iterative Shift-and-Add Multiplier + Restoring Divider

- Implementation: one 64-bit adder, 130-bit accumulator, shift register.
- Multiplier: 64 cycles, 1 bit/cycle.
- Divider: 64 cycles (restoring) or ~64 cycles (non-restoring).
- Area: very small.
- PROPOSAL-class baseline for comparison only.

### A2. Booth-Radix-4 Multiplier + Iterative Divider

- Multiplier: 32 partial products, Wallace/Dadda reduction, 2-stage pipelined, 2-cycle latency, 1/cycle throughput.
- Divider: 64-cycle non-restoring.
- Area: small-to-medium.
- Used in many embedded RV cores (e.g., SiFive E-class predecessors).

### A3. Pipelined Radix-4/8 Booth + Radix-4 SRT Divider

- Multiplier: 2–3 stage pipeline, 1/cycle issue, latency 2–3 cycles.
- Divider: radix-4 SRT, ~16 cycles, ~1 per 16 cycles throughput.
- Area: medium.
- Used in superscalar cores (e.g., BOOM-family, Ariane-derived).

### A4. Fully Combinational Array Multiplier + Radix-16 SRT Divider

- Multiplier: 64×64 → 128, single cycle, large area.
- Divider: 4–8 cycles, 1 per 4–8 cycles throughput.
- Area: large.
- Used in high-frequency superscalar out-of-order cores.

### A5. Shared/Vector MUL-DIV Unit (per-cluster)

- A single MUL/DIV unit is shared across N cores, accessed via a reservation station.
- Saves replicated area; increases latency and contention.
- Used in some throughput-oriented many-core designs.

## Alternative Designs

### B1. 2-Stage Pipelined Radix-4 Booth Multiplier

- 17 partial products reduced via 4:2 compressor tree.
- Two pipeline stages: partial-product reduction, then final carry-propagate add.
- Latency 2 cycles, throughput 1/cycle.
- Divider: 32-cycle non-restoring (radix-2 non-restoring with early-exit optimization).

### B2. 3-Stage Pipelined Radix-8 Booth Multiplier

- 11 partial products.
- Latency 3 cycles, throughput 1/cycle.
- Smaller critical path than B1, higher area.

### B3. Iterative Multiplier with Multi-Cycle Variable Latency

- Single 64×64 multiplier reused across MUL/MULH/MULHU by selecting the relevant output bits.
- Latency 4–5 cycles, 1/cycle throughput.
- Smaller area than B1 but longer latency.

### B4. Radix-4 SRT Divider with Pipelined Issue

- 16-cycle latency, fully pipelined so back-to-back divides (with different operands) are allowed.
- Larger area, more verification complexity.

### B5. Newton-Raphson Divider with Hardware Reciprocal Iteration

- ~4–6 cycles for 32-bit reciprocal, then 1 multiply.
- Lowest divide latency, but variable and dependent on operand class.
- Complex verification (convergence proofs required).

### B6. Two's-Complement Array Divider (Combinational)

- Single-cycle 64-bit divide.
- Extremely large area (~64× of a 64-bit multiplier).
- Likely unacceptable for 128-core replication.

## Comparison

| Design | MUL Latency | MUL Throughput | DIV Latency | DIV Throughput | Relative Area | Verification Complexity |
|--------|-------------|----------------|-------------|----------------|---------------|-------------------------|
| A1. Shift-add + restoring | 64 | 1/64 | 64 | 1/64 | 1× | Low |
| A2. Booth-r4 + NR div    | 2  | 1/1   | 32 | 1/32 | ~3–4× | Low–Medium |
| A3. Pipelined r4/r8 + SRT-4 | 2–3 | 1/1 | 16 | 1/16 | ~5–7× | Medium |
| A4. Combinational + SRT-16  | 1  | 1/1 | 4–8 | 1/8  | ~10–15× | High |
| B1. 2-stage r4 + NR-32    | 2  | 1/1   | 32 | 1/32 | ~3–5× | Low–Medium |
| B4. Pipelined SRT-4        | n/a | n/a | 16 | 1/16 | adds ~3–4× | Medium |
| B5. Newton-Raphson        | 1 (MUL) | 1/1 | 4–6 | 1/4–6 | ~6–8× | High |
| B6. Combinational array   | 1  | 1/1   | 1  | 1/1  | ~50× | Medium |

PROPOSAL: A representative B1+B4 hybrid is a 2-stage pipelined Radix-4 Booth multiplier paired with a pipelined Radix-4 SRT divider. This is a reasonable starting point pending synthesis-driven PPA feedback.

## Advantages

- A 2-stage pipelined Radix-4 Booth multiplier offers 1/cycle throughput at modest area, suitable for a replicated 128-core design.
- A pipelined Radix-4 SRT divider (or a non-restoring iterative divider with early-exit) meets the latency needs of most workloads without dominating area.
- Deterministic latencies (vs. Newton-Raphson) simplify pipeline scheduling, forwarding, and verification.
- Radix-4 Booth and SRT-4 are well-understood and have reference implementations in academic and open-source RISC-V cores.

## Disadvantages

- 16-cycle SRT-4 divide is still slow for workloads dominated by large-integer arithmetic (RSA, big-integer math).
- Combinational or Newton-Raphson dividers reduce latency significantly but at unacceptable area/verification cost for 128-core replication.
- A non-restoring iterative divider has the lowest area but penalizes every divide by ~32 cycles, which can be felt in hash-table probing, parser/lexer dispatch, and some interpreters.
- Booth encoding complicates verification of signed/unsigned correctness (MULH vs. MULHSU vs. MULHU).

## XH-1 Considerations

- ASSUMPTION: XH-1 is a 128-core design with a relatively short pipeline (TBD by `pipeline.md`). The MUL/DIV unit must fit in a small per-core area budget and the EX stage latency budget.
- ASSUMPTION: The design targets a balance of general-purpose and HPC-adjacent workloads; therefore a moderately fast (but not the fastest) divider is acceptable.
- PROPOSAL: Adopt a 2-stage pipelined Radix-4 Booth multiplier (MUL, MULH, MULHSU, MULHU, MULW) and a 32-cycle non-restoring iterative divider with early-exit optimization.
- The multiplier is sized to produce the full 128-bit product so that MULH/MULHU selection requires only output muxing, not a separate datapath.
- The W-variants (MULW, DIVW, etc.) reuse the lower 32 bits of the 64-bit datapath with sign-extension at the output.

### Instruction Coverage

- MUL/MULH/MULHSU/MULHU: supported.
- DIV/DIVU/REM/REMU: supported, with corner cases (÷0, INT_MIN/-1, signed overflow per spec) handled explicitly.
- MULW/DIVW/DIVUW/REMW/REMUW: supported via shared datapath.

### Edge Cases

- Division by zero: returns -1 for DIV, x for DIVU, per RISC-V spec; the unit must produce the architecturally specified result without exception.
- Signed overflow (INT64_MIN / -1): returns INT64_MIN for DIV, 0 for REM.
- These cases are common sources of bugs and require explicit test coverage.

## 128-Core Scalability

- Area: replicating 128 copies of even a moderately sized MUL/DIV unit is a significant die-level cost. The chosen design (B1+B4 baseline) is estimated at <1–2% of a typical small RV core area, but 128× replication is non-trivial.
- Floorplanning: a regular MUL/DIV layout that mirrors across cores is preferred to avoid routing asymmetry that would break clock distribution.
- Voltage/Frequency: a deeply pipelined MUL/DIV is more resilient to voltage droop; this is an advantage for 128-core operation.
- Contention: there is no inter-core contention for the MUL/DIV unit (per-core replication); the only contention is intra-core (two dependent divides in flight).
- Test/DFT: 128 instances of the MUL/DIV unit must be tested; a scan-friendly, fully synchronous design with no asynchronous reset paths inside the iterative divider is preferable.

## Performance Considerations

- For general-purpose code, MUL/DIV is rarely the bottleneck; the chosen 2-cycle MUL latency matches typical issue-to-use distances.
- For cryptography (AES SubBytes via GF(2⁸), polynomial multiplies, RSA), MUL throughput is the key metric — 1/cycle is the floor for acceptable performance.
- For hash tables and interpreters, DIV latency matters more than throughput; a 32-cycle divider is acceptable but not ideal.
- For 64-bit polynomial multiplication, MULH throughput is the key metric.
- For 32-bit integer code, the W-variants are the hot path; reusing the 64-bit datapath with muxed operands is acceptable.

## Area Considerations

- ASSUMPTION: A 64×64 → 128-bit Radix-4 Booth multiplier with a 4:2 compressor tree and 2-stage pipelined final adder occupies roughly 0.05–0.10 mm² in a typical 7nm process.
- ASSUMPTION: A 32-cycle non-restoring iterative divider occupies roughly 0.02–0.05 mm².
- PROPOSAL: Total MUL/DIV area target: <0.15 mm² per core. 128× replication: ~20 mm². INSUFFICIENT EVIDENCE to refine this without a technology file.
- The 4:2 compressor tree is more area-efficient than a Wallace tree for radix-4.
- Sign-extension and zero-extension muxes for MULW are negligible area.

## Power and Energy Considerations

- A 64×64 multiplier tree has high switching activity; clock gating when the unit is idle is essential.
- The iterative divider has lower average power than a fully combinational divider, but its long residency increases leakage energy per operation.
- Power gating: at 128 cores, a per-core power-gate for the MUL/DIV unit is worth considering if idle periods dominate.
- Energy per multiply: dominated by the compressor tree; energy scales roughly with the number of partial products.
- Energy per divide: dominated by the 32-cycle residency; techniques to short-circuit trailing zeros in the dividend (early-exit) can reduce energy in common cases.

## Implementation Considerations

- Use synchronous, single-clock-domain design inside the unit.
- Avoid asynchronous resets inside the iterative divider; use synchronous reset only at the start of an operation.
- Multiplier carry-propagate adder should be a Kogge-Stone or Han-Carlson adder for speed, with a Brent-Kung fallback if area is tight.
- Divider quotient/remainder registers are 64 bits each, with an extra bit for the iterative sign.
- Microarchitectural state machine is small and well-suited to a one-hot or binary-encoded FSM.
- Output muxing for MUL/MULH/MULHSU/MULHU/MULW is a small mux tree, not a separate datapath.
- Booth encoding produces 33 partial products for radix-4 of a 64-bit operand; reduction to 2 operands via compressor tree.

## Verification Considerations

- Formal verification of the multiplier compressor tree + final adder is feasible with bounded model checkers and is recommended.
- Directed tests for division edge cases (÷0, INT_MIN/-1, dividend=d divisor=1, dividend=0 divisor=x, all-ones, alternating bits).
- Randomized differential testing against a software reference (e.g., a GCC-compiled test harness running on Spike or QEMU) is recommended.
- Coverage of all 4 MUL variants and 4 MULH variants plus the W-variants.
- 128-core DFT: scan stitching should be reviewed to ensure no long scan chains between the iterative divider and surrounding logic cause hold-time issues.
- Reference models: a Python or C++ golden model for the entire RV64M ISA is recommended and reusable across all 128 cores.
- UVM or cocotb-based testbenches: the unit is small enough that a single high-quality testbench can be reused.

## Software Implications

- Compilers will emit MUL freely; no software changes are required.
- Division by a constant is often transformed by the compiler into a magic-number multiply; the choice of MUL/DIV design therefore disproportionately affects runtime divide performance.
- For languages with software-emulated 128-bit integers (e.g., __int128 in C/C++), the compiler will emit MULH/MULHU sequences; MULH latency and throughput become important.
- Crypto libraries (libsodium, OpenSSL, mbedTLS) often use Karatsuba or Montgomery multiplication, which benefit from 1/cycle MULH throughput.
- JavaScript engines and language runtimes may issue frequent DIVs for tagged-value unpacking; a slow divider increases interpreter overhead.

## Recommendation

PROPOSAL: Adopt a 2-stage pipelined Radix-4 Booth multiplier paired with a 32-cycle non-restoring iterative divider (with early-exit optimization for the dividend). Provide pipelined throughput of 1 MUL per cycle and 1 DIV per 32 cycles.

Rationale:
- Best balance of area, energy, and performance for 128-core replication.
- Deterministic, fully synchronous design simplifies verification and DFT.
- 1/cycle MUL throughput meets crypto and HPC-adjacent needs.
- 32-cycle DIV latency is acceptable for general-purpose workloads; can be revisited if profiling shows a hotspot.

RECOMMENDATION (with caveats): If early workload analysis (TBD) shows that divide latency is a bottleneck, consider upgrading the divider to a pipelined Radix-4 SRT (16 cycles) at ~3–4× the divider area. Do not adopt a Newton-Raphson divider unless profiling evidence strongly supports it, due to verification complexity.

RECOMMENDATION: Do not adopt a fully combinational array divider or fully combinational multiplier for the replicated 128-core design. The area cost is not justified by the latency benefit.

## Confidence

- Direction of recommendation: MEDIUM. The general design class is well-established; specific numbers (area, latency, energy) require synthesis runs against a target technology library.
- Quantitative area/power numbers: LOW. No measurements exist in the repository; all such numbers in this document are estimates.
- Verification strategy: HIGH. The recommended approach (formal on the multiplier, directed + randomized for the divider) is standard practice.
- Edge-case correctness: HIGH. The RISC-V spec is explicit and well-tested across many cores.

## Open Questions

- What is the EX-stage latency budget? (Depends on `pipeline.md`.)
- What is the target frequency and process node? Determines whether 1-cycle or 2-cycle MUL is feasible.
- Is the design in-order or out-of-order? Out-of-order execution can hide divide latency; in-order cannot.
- Will the MUL/DIV unit share an issue port with the ALU, or have a dedicated issue port? (Likely shared, but TBD.)
- Is there a future F/D extension? If so, the integer MUL/DIV unit may also need to handle FP-to-int conversions or FP reciprocal iterations.
- What is the workload mix expected? Scientific (HPC) vs. general-purpose vs. embedded?
- Should the MUL/DIV unit be power-gated when idle? At 128 cores, idle probability may be high.
- Should the divider support a "fast-path" for division by a small constant (e.g., compiler-inserted reciprocal multiply hint)?

## Sources

- The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA — defines M-extension semantics. (Documented in standard ISA references; no specific URL is cited here per the no-fabrication rule.)
- Hennessy and Patterson, "Computer Architecture: A Quantitative Approach" — covers MUL/DIV trade-offs.
- Parhami, "Computer Arithmetic: Algorithms and Hardware Designs" — covers multiplier and divider algorithms in depth.
- Open-source RISC-V cores (e.g., Rocket, BOOM, Ariane) for design-class references. Specific measurements, layouts, and PPA numbers: INSUFFICIENT EVIDENCE in the current XH-1 repository.
- No quantitative claims in this document are derived from measurements; all are estimates unless explicitly labeled otherwise.
