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XH-1 memory ordering model has not yet been defined. The repository contains no source artifacts, RTL, ISA extension proposals, or reference implementations that establish a memory consistency model for XH-1.\n\n## Abstract\n\nMemory ordering defines the rules by which loads and stores issued by one or more cores become visible to other cores in the system. For a 128-core RISC-V processor, the choice of memory model — and the hardware mechanisms that enforce it — is one of the most consequential architectural decisions, affecting correctness, performance, area, power, scalability, and software portability. This document surveys the design space, identifies the candidate models available within the RISC-V ISA framework, examines alternative hardware enforcement strategies, and frames the open questions for XH-1. No recommendation is made because the repository context does not yet establish pipeline style, coherency protocol, or interconnect topology — all of which constrain the memory ordering decision.\n\n## Research Question\n\nWhat memory consistency model and hardware ordering mechanism should XH-1 adopt, given:\n\n1. A 128-core replication target\n2. The RISC-V ISA baseline\n3. The need to balance software portability against hardware implementation cost\n4. Unknown microarchitecture style (in-order vs. out-of-order is not established in the repository)\n5. The relationship to the cache coherency protocol (defined in `cache-coherency.md`, currently SOON)\n\n## Background\n\n### Memory Consistency Models — Terminology\n\nPROPOSAL — Use the following working taxonomy in this document:\n\n- **Sequential Consistency (SC)**: All cores observe a single total order of memory operations that respects each core's program order.\n- **Total Store Order (TSO)**: Loads may bypass stores; stores from one core are seen in order by all cores. Used by x86.\n- **Relaxed / Weak Memory Models**: Many orderings are allowed; fences (barriers) are required to enforce constraints. Used by ARM, RISC-V, and PowerPC.\n- **Release Consistency (RC) / RCO / RCpc / RCsc**: A family of models with different fence semantics. Used by academic designs and the basis for much of the C11/C++ memory model formalization.\n\n### The RISC-V \"RVWMO\" Model\n\nFACT — The RISC-V ISA specification defines the **RISC-V Weak Memory Ordering (RVWMO)** model as the baseline. Under RVWMO:\n\n- Loads and stores to the same address from the same hart are ordered.\n- A store followed by a load to a *different* address may be reordered.\n- The `FENCE` instruction is used to enforce orderings. The base FENCE provides `pred` (predecessor) and `succ` (successor) bits covering device I/O (I), memory reads (R), and memory writes (W). Device ordering follows a stronger \"Preserved over Higher Privilege and PMA\" model (PostModel).\n- The optional `Ztso` extension provides **RVTSO**, which gives x86-like TSO semantics with a relaxed form of the FENCE.\n\nASSUMPTION — RVWMO + the Ztso optional extension is the available ISA-level model space that XH-1 must select from. (The repository does not document any custom ISA extensions, so XH-1 is assumed to stay within ratified RISC-V.)\n\n### Why Memory Ordering is Hard at 128 Cores\n\nOPEN QUESTION — The repository does not establish:\n- Whether XH-1 is a single die, multi-die package, or chiplet-based system\n- The interconnect topology (mesh, ring, crossbar, NoC, etc.)\n- Whether coherence is directory-based, broadcast-based, or hybrid\n- The private-vs-shared L2/L3 split\n- The memory-side directory or snoop filter organization\n\nThese decisions have direct bearing on which ordering mechanisms are feasible. Any hardware ordering scheme (invalidation queues, store buffers, fence acknowledgments, coherence-based ordering) must be analyzed in the context of these unknowns.\n\n## Existing Approaches\n\n### Approach A — RISC-V RVWMO (Baseline)\n\nThe standard weak memory model provided by the RISC-V ISA. Requires implementation of `FENCE`, `FENCE.I`, and the I/O ordering semantics.\n\n**Mechanism**: Architecture permits aggressive reordering. Hardware typically uses:\n- Store buffers with forwarding\n- Load-load reordering queues\n- Coherence-based ordering: stores become visible at coherence invalidation/upgrade points\n- Fence implementation via global acknowledgment counters or by draining reorder queues\n\n### Approach B — RVWMO + Ztso Extension\n\nAdds RVTSO. Software that requires x86-like ordering can avoid fences in many cases. Still RISC-V compliant.\n\n**Mechanism**: Stores from one hart are serialized in the interconnect; loads may still pass earlier stores to different addresses.\n\n### Approach C — Sequential Consistency (SC)\n\nAll operations observed in a single global order respecting program order. Simplest software model; most expensive hardware.\n\n**Mechanism**: Typically requires store-buffer draining on loads, broadcast-based coherence, and conservative replay mechanisms. Implementation cost is high in general; whether it is \"very costly\" specifically at 128 cores is workload- and topology-dependent and is treated here as a hypothesis, not a known result.\n\n### Approach D — Release Consistency variants (RCsc, RCpc, RCO)\n\nAcademic models where release/acquire ordering is cheap but stronger fences are required for full memory ordering. Basis of C11/C++ model.\n\n**Mechanism**: Only release/acquire fences require acknowledgment; acquire-only loads are cheap. Alignment with C11 is a strong software benefit. These variants are not part of the ratified RISC-V ISA, so adoption would require a custom ISA extension.\n\n## Alternative Designs\n\n### Hardware Ordering Mechanisms (to be evaluated once coherency and interconnect are known)\n\nPROPOSAL — The following mechanisms should be considered for fence/ordering enforcement:\n\n1. **Invalidation-acknowledgment fences** — A fence blocks until all outstanding coherence requests have been acknowledged. Simple and common; scaling impact depends on directory hop count, aggregate invalidation traffic, and invalidation filter structure.\n\n2. **Per-core store-buffer drain fences** — A fence stalls the issuing core until its store buffer is empty and all stores have been globally observed. Predictable latency; serializes through the coherence fabric.\n\n3. **Tournament / Token-based fences** — Fences acquire a global token or wait for a \"fence epoch\" counter. Avoids worst-case drain, but adds global state.\n\n4. **FIFO coherence ordering** — Leverages the in-order completion of coherence transactions to provide ordering without explicit fences. Requires in-order interconnect, which conflicts with typical latency-optimized NoC designs.\n\n5. **Time-to-live / epoch schemes** — Each coherence request carries an epoch tag; ordering is enforced at the L2/L3 directory by queueing requests by epoch.\n\n6. **Speculative load reordering with rollback** — Loads can execute speculatively past stores; on conflict, the load is replayed. Common in high-performance out-of-order cores (e.g., IBM POWER).\n\nASSUMPTION — XH-1's microarchitecture style is not yet established. If out-of-order, the \"speculative load reordering with rollback\" category becomes a candidate. If in-order, mechanism choices narrow considerably.\n\n## Comparison\n\n| Property | SC | RVWMO | RVWMO + Ztso | RC variants |\n|----------|----|----|----|----|\n| Software ease | Highest | Medium | Medium-High | Low-Medium |\n| Hardware cost | Highest | Low | Low-Medium | Low |\n| Performance headroom | Lowest | Highest | High | High |\n| Fence latency | N/A | Variable | Variable | Variable |\n| Verification cost | Lowest in principle | High | High | High (likely highest) |\n| C11/C++ alignment | Approximate | Approximate | Weak | Direct |\n| 128-core scalability | Poor (hypothesis) | Good (claim) | Good (claim) | Good (claim) |\n\nINSUFFICIENT EVIDENCE — Quantitative fence-latency, coherence-traffic, and scalability numbers for XH-1 are unavailable. Several rows above contain qualitative judgments rather than measured results, and the \"128-core scalability\" and \"verification cost\" rows reflect general literature consensus, not XH-1 measurements.\n\n## Advantages\n\n### RVWMO (Baseline)\n- **Lowest hardware cost** of all candidates for the base case — most orderings are simply not enforced.\n- **Maximum performance** potential — reordering is unconstrained.\n- **Familiar** to RISC-V software ecosystem (Linux, RISC-V GCC, LLVM).\n- **Standardized** — concrete compliance test suite exists.\n\n### RVWMO + Ztso\n- **x86-like TSO** for software that benefits from stronger ordering.\n- **Backwards compatible** — software not using Ztso still runs correctly under RVWMO.\n- **Modest hardware cost** — primarily requires store-store ordering at the coherence layer.\n\n### Release Consistency Variants\n- **Excellent fit for C11/C++** atomics — acquire/release are the most-used fence types in real code.\n- **Cheapest common case** — acquire and release can be implemented with lightweight mechanisms.\n- **Hardware cost is concentrated on the rare case** of full seq_cst fences.\n\n## Disadvantages\n\n### RVWMO (Baseline)\n- **Fence latency depends on coherence round-trip** — at 128 cores, fence latency is expected to be high because global acknowledgment must traverse the coherence fabric. Specific cycle counts: INSUFFICIENT EVIDENCE.\n- **Verification complexity is high** — many legal reorderings; the litmus-test failure surface is large.\n- **Software burden** — kernel and runtime code must insert fences correctly.\n\n### RVWMO + Ztso\n- **Two consistency models in one chip** — adds documentation, validation, and software education cost.\n- **In-flight mixing** of ordering regimes in the same software is hard to reason about.\n\n### Release Consistency Variants\n- **Non-standard for RISC-V** — would require a custom ISA extension. Cannot be recommended without a strong software-side driver.\n- **Verification cost is high** in general because of subtle fence semantics; whether it is the \"highest\" among candidates is a claim about the literature, not a measured XH-1 result.\n\n### Sequential Consistency\n- **Performance cost is severe in the general case** — every load may stall on store-buffer drain; whether this is \"severe at 128 cores\" specifically is workload- and topology-dependent and is not established by the repository.\n- **No selective escape valve** — software cannot opt out of the strongest model.\n- **Does not match RISC-V ecosystem expectations** — surprising to RISC-V software developers.\n\n## XH-1 Considerations\n\nOPEN QUESTION — The following XH-1-internal questions are unresolved by the repository:\n\n1. Is XH-1's pipeline in-order or out-of-order?\n2. What is the coherence protocol (MOESI, MESI, directory-based, broadcast)?\n3. Is the interconnect a NoC, ring, or crossbar? Does it preserve in-order delivery of coherence responses?\n4. What is the expected working set of a typical hart — does streaming-store optimization matter?\n5. Does XH-1 target HPC, server, embedded, or mixed workloads? (Workload affects fence frequency.)\n6. Is XH-1 a research vehicle (where SC is acceptable for simplicity) or a product (where RVWMO compliance is mandatory)?\n7. Does the memory map use non-coherent regions (e.g., DMA, I/O) that interact with the ordering model?\n\nASSUMPTION — If XH-1 targets RISC-V ecosystem compatibility (Linux, RISC-V GCC, RISC-V LLVM), then RVWMO is mandatory. Ztso may optionally be added for x86-software porting convenience.\n\n## 128-Core Scalability\n\nPROPOSAL — Scalability analysis of each candidate at 128 cores. Quantitative figures: INSUFFICIENT EVIDENCE. The qualitative observations below are hypotheses grounded in general literature, not XH-1 measurements.\n\n### Fence Latency\n- **Fence global acknowledgment** latency is bounded below by the worst-case coherence round-trip time. In a 128-core system, this can plausibly reach many tens of cycles in a NoC and higher in a ring or multi-hop topology; specific XH-1 figures: INSUFFICIENT EVIDENCE.\n- **Store-buffer drain** latency is approximately proportional to the store buffer depth and the time to invalidate all sharers.\n- **Token / epoch fences** may scale better because they avoid draining the entire coherence fabric — they synchronize at a logical epoch boundary.\n\n### Coherence Traffic\n- **RVWMO fences** generate invalidation or acknowledgment traffic that competes with normal coherence traffic. The magnitude depends on directory organization, snoop-filter effectiveness, and share-set size.\n- **SC at 128 cores** can plausibly saturate a directory-based interconnect because every load's coherence transaction may stall pending store ordering; this is a hypothesis, not a measured XH-1 result.\n- **RC variants** concentrate traffic on the fence path only.\n\n### Verification Scalability\n- **State-space explosion**: at 128 cores, the number of concurrently observable memory operations grows combinatorially in the unmitigated model. Memory-ordering verification is a known scaling bottleneck in the literature, and the repository does not establish what reduction or abstraction techniques XH-1 will employ.\n- **RC variants** are commonly cited as among the hardest to verify because of subtle fence interactions; whether they are hardest in the absolute sense is a literature claim, not an XH-1 measurement.\n- **SC is easiest to verify in principle** because it admits fewer legal behaviors, but worst in performance.\n\nINSUFFICIENT EVIDENCE — No quantitative fence-latency or coherence-traffic data is available for XH-1. Estimates cannot be made without knowing the interconnect.\n\n## Performance Considerations\n\nPROPOSAL — Performance-impact dimensions to evaluate:\n\n1. **Steady-state IPC** for memory-bound workloads — qualitatively, RVWMO permits the most reordering and SC the least; XH-1-specific IPC: INSUFFICIENT EVIDENCE.\n2. **Fence latency** — measured as cycles from fence issue to fence completion. Dominant for synchronization-heavy code. XH-1-specific: INSUFFICIENT EVIDENCE.\n3. **Scalable synchronization** — how the model interacts with lock implementations, RCU, and atomic primitives.\n4. **Load-use latency** — whether loads can bypass earlier stores (allowed in RVWMO and TSO, not in SC).\n5. **Coherence miss rate** interaction — does the ordering model inflate or deflate cache-line ping-pong? Model-dependent; XH-1-specific: INSUFFICIENT EVIDENCE.\n\nASSUMPTION — For HPC workloads with high-fence frequency (e.g., MPI, OpenMP, lock-heavy code), even small differences in fence latency will dominate. For server workloads with mixed locking, the cost of fences is amortized over longer critical sections. No XH-1 workload profile is documented in the repository.\n\n## Area Considerations\n\nPROPOSAL — Qualitative area cost of ordering mechanisms:\n\n| Mechanism | Approximate area cost per core |\n|-----------|-------------------------------|\n| Store buffer with forwarding | Small (few entries × cache-line width) |\n| Load-load reordering queue | Small to medium (grows with IPC and reorder depth) |\n| Fence-acknowledgment counter | Negligible (per-core counter) |\n| Global epoch / token state | Medium (one per chip, not per core) |\n| Speculative load reorder + rollback | Large (load-load queue, replay logic) |\n\nINSUFFICIENT EVIDENCE — All descriptions above are qualitative. Precise XH-1 area figures (in gates, µm², or mm²) are unavailable.\n\nPROPOSAL — At 128 cores, even small per-core area costs multiply by 128. Global state (epoch counters, fence acknowledgers) is O(1) per chip and therefore becomes attractive on a per-core basis, but requires careful analysis of critical-path and clock-distribution impact, which is not established by the repository.\n\n## Power and Energy Considerations\n\nPROPOSAL — Qualitative energy implications:\n\n- **Fences** generate global coherence traffic — energy cost scales with the number of cores that must acknowledge. The aggregate chip-level energy per fence is therefore expected to grow with core count.\n- **Speculative load reordering** wastes energy on rollback when a violation is detected.\n- **Strong ordering models** keep more coherence state in flight (more invalidations, more retries).\n- **RVWMO** with lightweight fences (when software permits) is the lowest-energy regime in the general case.\n\nINSUFFICIENT EVIDENCE — The earlier text claimed that a 100 pJ-per-core fence at 16 cores costs 800× at 128 cores in the worst case (if all cores must acknowledge). This multiplication assumed 100 pJ is a measured or even a defensible per-core figure, which is not established by the repository or by a cited source. The 100 pJ figure is removed. A defensible claim is only that per-fence chip-level energy is expected to grow with the number of acknowledging cores; quantitative XH-1 values: INSUFFICIENT EVIDENCE.\n\n## Implementation Considerations\n\nPROPOSAL — Implementation order of dependencies (the repository does not establish these, but the research area suggests the following):\n\n1. Define coherency protocol → `cache-coherency.md`\n2. Define interconnect topology → not yet in repository\n3. Define memory hierarchy → `memory-hierarchy.md`\n4. Define memory ordering model → this document\n5. Define atomic primitives → `atomics.md`\n\nASSUMPTION — The Ztso extension is a small RTL delta over RVWMO. The dominant implementation cost is verification, not area. No RTL exists in the repository to substantiate even a relative area claim, so this is treated as a plausible qualitative statement rather than a measured result.\n\nOPEN QUESTION — Does XH-1 have a coherent accelerator fabric or non-coherent IO (e.g., CXL, DMA engines)? If so, the memory ordering model must define how these agents interact, and the repository does not currently do so.\n\n## Verification Considerations\n\nPROPOSAL — Verification challenges:\n\n- **Litmus tests**: A standard RISC-V litmus test suite is available externally; whether XH-1 will adopt it as-is or define a custom suite is OPEN.\n- **State-space explosion**: 128 cores × N outstanding operations produces a combinatorial unmitigated state space. The repository does not establish whether XH-1 will use state-space reduction, abstraction, bisimulation, or formal methods. Any specific XH-1 claim: INSUFFICIENT EVIDENCE.\n- **Fence semantics**: Each fence variant must be exhaustively tested at corner cases (interrupts, exceptions, MMIO).\n- **Coherence-ordering interaction**: The ordering model must be checked against the chosen coherence protocol for consistency. This check cannot be performed until the coherence protocol is defined.\n\nINSUFFICIENT EVIDENCE — No XH-1 verification infrastructure, formal spec, or litmus-test set is documented in the repository.\n\nASSUMPTION — RVWMO is the most documented and tested model for RISC-V. Ztso is a small addition. SC and RC variants would require custom formal infrastructure. These are qualitative claims about ecosystem maturity, not XH-1-specific measurements.\n\n## Software Considerations\n\nPROPOSAL — Software-side impact:\n\n- **Linux kernel**: Designed for weak memory models with appropriate fences. Compatible with RVWMO.\n- **C11/C++ atomics**: Map cleanly onto release/acquire semantics. Compatible with RVWMO and with RC variants.\n- **x86 software ports**: Benefit from Ztso for fewer fences.\n- **OpenSHMEM, MPI shmem**: Often assume TSO-like ordering; Ztso helps.\n- **HPC codes with hand-rolled atomics**: Highly sensitive to fence latency.\n\nASSUMPTION — XH-1 will run RISC-V Linux. The kernel's memory model expectations must be satisfied by XH-1's hardware ordering rules. The repository does not document whether Linux is in fact the target.\n\n## Recommendation\n\nINSUFFICIENT EVIDENCE to make a final recommendation.\n\nThe repository does not yet establish:\n- Pipeline microarchitecture\n- Coherence protocol\n- Interconnect topology\n- Workload target\n\nA recommendation can be made only after the following documents in the memory research area are filled in: `memory-architecture.md`, `cache-coherency.md`, `memory-hierarchy.md`. Without these, any model selection is premature.\n\nPROPOSAL — Tentative default pending more repository context:\n\n1. **Baseline**: RVWMO (mandatory for RISC-V ecosystem compatibility, if Linux is the target OS).\n2. **Optional add-on**: Ztso extension for x86-software porting convenience and modest hardware cost, contingent on verification cost being acceptable.\n3. **Avoid**: SC, custom RC variants, unless a strong workload or research driver emerges.\n4. **Defer to**: `cache-coherency.md` for the coherence-side ordering mechanism.\n\n## Confidence\n\n| Topic | Confidence | Reason |\n|-------|------------|--------|\n| RVWMO is the RISC-V baseline | High | Ratified ISA spec |\n| Ztso is a small optional extension | High | Ratified extension |\n| SC has high implementation cost | High | General literature consensus |\n| SC specifically impractical at 128 cores | Low | General claim, not XH-1-measured; workload- and topology-dependent |\n| Per-fence energy scales with acknowledging-core count | Medium | Logical consequence; no measurement |\n| Quantitative per-fence energy at 128 cores | None | INSUFFICIENT EVIDENCE |\n| Verification is hardest for RC variants | Low–Medium | Literature claim, not XH-1-measured |\n| XH-1 should adopt RVWMO | Low | Repository context not yet sufficient |\n| XH-1 should adopt RVWMO + Ztso | Low | Same |\n\n## Open Questions\n\n1. What is XH-1's microarchitecture style (in-order vs. out-of-order)?\n2. What coherence protocol and directory organization will XH-1 use?\n3. What is the interconnect topology, and does it preserve coherence-response order?\n4. What workloads are targeted — HPC, server, embedded?\n5. Does XH-1 include non-coherent agents (DMA, CXL, accelerators)?\n6. Is XH-1 a research vehicle, a prototype, or a product?\n7. What is the expected fence frequency in target software?\n8. What is the verification methodology — formal, simulation, or hybrid?\n9. Will XH-1 use the standard RISC-V litmus-test suite or define a custom one?\n10. Does XH-1 require compatibility with x86-software-only ports? (Drives Ztso inclusion.)\n11. What fence-latency, area, and energy budgets are acceptable for the target envelope?\n12. What is the state-space reduction or formal-verification strategy, if any?\n\n## Sources\n\nINSUFFICIENT EVIDENCE — The XH-1 Research repository does not yet contain source material specific to memory ordering. No citations, papers, or measurements can be honestly attributed to XH-1.\n\nExternal ISA-level facts cited above (RVWMO, Ztso, FENCE instruction semantics) are drawn from the publicly ratified RISC-V ISA specification, which is the source of truth for the ISA-level memory model. The RISC-V ISA specification is the canonical reference; no specific paper, version, or page reference is provided because the XH-1 repository does not document which revision is being targeted.\n\nINSUFFICIENT EVIDENCE — All quantitative claims about fence latency, area, power, energy, and verification cost at the XH-1 level have been removed or flagged. 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