4.2 KiB
4.2 KiB
SPARC V9 ISA Reference
Reference documentation for the SPARC V9 instruction set as implemented in ReviveSparc.
Overview
The SPARC V9 architecture is a 64-bit RISC ISA developed by Sun Microsystems and standardized by SPARC International. ReviveSparc implements the full SPARC V9 specification, including the VIS (Visual Instruction Set) extensions.
Key Features
- 64-bit integer and floating-point registers
- 32 general-purpose registers (register windowed)
- 32 floating-point registers (quad-precision capable)
- Delayed branching with annulment
- Register windowing with 8 global + up to 32 windowed registers
- Precise exceptions and multiple trap levels
Instruction Set Categories
Integer Instructions
ADD Add ADDcc Add and modify CC
AND And ANDcc And and modify CC
OR Or ORcc Or and modify CC
XOR Exclusive Or XORcc Exclusive Or and modify CC
SUB Subtract SUBcc Subtract and modify CC
MULX Multiply Extended UDIVX Unsigned Divide Extended
SDIVX Signed Divide Extended
SLL Shift Left Logical SRL Shift Right Logical
SRA Shift Right Arithmetic
Load/Store Instructions
LDUB Load Unsigned Byte
LDSB Load Signed Byte
LDUH Load Unsigned Halfword
LDSH Load Signed Halfword
LDW Load Word
LDX Load Doubleword
STB Store Byte
STH Store Halfword
STW Store Word
STX Store Doubleword
LDF Load Floating-point
LDDF Load Double Floating-point
STF Store Floating-point
STDF Store Double Floating-point
Branch Instructions
Bcc Branch on Condition
BPcc Branch on Condition (Predicted)
BPr Branch on Register
CALL Call and Link
RETT Return from Trap
JMPL Jump and Link
RETURN Return from Subroutine
Floating-Point Instructions
FADDs FP Add (single)
FADDd FP Add (double)
FSUBs FP Subtract (single)
FSUBd FP Subtract (double)
FMULs FP Multiply (single)
FMULd FP Multiply (double)
FDIVs FP Divide (single)
FDIVd FP Divide (double)
FSQRTs FP Square Root (single)
FSQRTd FP Square Root (double)
F CMPs FP Compare (single)
F CMPd FP Compare (double)
VIS Instructions
FPACK16 Pack 16-bit
FPACK32 Pack 32-bit
FALIGNDATA Align Data
FEXPAND Expand
FMUL8x16 Multiply 8-bit by 16-bit
FMUL8x16AU Multiply 8-bit by 16-bit (unsigned)
FMUL8x16AL Multiply 8-bit by 16-bit (unsigned)
FMUL8SUx16 Multiply 8-bit Signed by 16-bit Unsigned
FMUL8ULx16 Multiply 8-bit Unsigned by 16-bit Unsigned
FMULD8SUx16 Multiply Double 8-bit Signed by 16-bit Unsigned
FMULD8ULx16 Multiply Double 8-bit Unsigned by 16-bit Unsigned
Register Windows
SPARC V9 uses register windows to optimize function call performance:
- 8 global registers (%g0 through %g7, where %g0 is always zero)
- Up to 32 register windows, each containing 16 registers
- Each window provides: 8 incoming (%i0-%i7), 8 local (%l0-%l7), 8 outgoing (%o0-%o7) — with overlap between adjacent windows
- The number of windows is implementation-dependent
Privileged Registers
| Register | Description |
|---|---|
| TPC | Trap PC (1-4) |
| TNPC | Trap Next PC (1-4) |
| TSTATE | Trap State (1-4) |
| TT | Trap Type (1-4) |
| TBA | Trap Base Address |
| PSTATE | Processor State |
| TL | Trap Level |
| PIL | Processor Interrupt Level |
| CWP | Current Window Pointer |
| CANSAVE | Cleanable Windows |
| CANRESTORE | Restorable Windows |
Trap Types
| TT Value | Trap Name | Description |
|---|---|---|
| 0x01 | instruction_access_exception | Memory access fault |
| 0x03 | instruction_access_error | Hardware error |
| 0x04 | illegal_instruction | Unimplemented instruction |
| 0x05 | privileged_operation | Trap in user mode |
| 0x06 | fp_disabled | FPU not enabled |
| 0x08 | clean_window | Register window spill needed |
| 0x09 | division_by_zero | Integer divide by zero |
| 0x20-0x2f | interrupt_vector | External interrupts |
| 0x60-0x7f | software_trap | ta instruction traps |
| 0x80 | data_access_exception | Data memory access fault |
| 0x82 | data_access_error | Data memory hardware error |