{
  "milestones": [
    {
      "version": "v0.0.1",
      "title": "Initial structure",
      "status": "released",
      "date": "Aug 2026",
      "items": [
        "Initial repository structure",
        "Moved source repository, issue tracker, and pull requests to self-hosted Git instance (git.revivesparc.com/Revivesparc/revivesparc)"
      ]
    },
    {
      "version": "v0.4.0",
      "title": "Full User-Space ISA",
      "status": "released",
      "date": "Jun 2026",
      "items": [
        "All SPARC V9 integer instructions implemented and verified",
        "All floating-point instructions (single, double, quad precision)",
        "VIS 1 and VIS 2 instruction set extensions",
        "Register window management (spill/fill traps)",
        "Comprehensive ISA test suite: ~12,000 test cases"
      ]
    }
  ],
  "future": [
    "SPARC V9e extensions — VIS 3, integer multiply-add, SHA-3 instructions",
    "Vector processing unit — SIMD engine inspired by SPARC64 VIIIfx",
    "PCIe host bridge — Allow real hardware peripherals in emulation",
    "GDB JTAG bridge — Connect GDB to FPGA-resident cores",
    "WebAssembly backend — Run ReviveSparc in the browser"
  ]
}