Revivesparc/main-website
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

* Initial

Browse Source
This commit is contained in:
al
2026-06-15 19:20:24 +02:00
commit 331f96efe4
22 changed files with 3840 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
about.html
+89
View File
@@ -0,0 +1,89 @@
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>About - ReviveSparc</title>
<link rel="stylesheet" href="style.css">
</head>
<body>
<div id="header">
<div class="inner">
<h1><a href="index.html">ReviveSparc</a></h1>
<p class="subtitle">An open-source OpenSPARC ISA reimplementation</p>
</div>
</div>
<div id="nav">
<div class="inner">
<ul>
<li><a href="index.html">Home</a></li>
<li><a href="about.html" class="active">About</a></li>
<li><a href="download.html">Download</a></li>
<li><a href="docs.html">Docs</a></li>
<li><a href="news.html">News</a></li>
<li><a href="roadmap.html">Roadmap</a></li>
<li><a href="screenshots.html">Screenshots</a></li>
<li><a href="community.html">Community</a></li>
<li><a href="sponsors.html">Sponsors</a></li>
</ul>
</div>
</div>
<div id="main">
<h2>About ReviveSparc</h2>
<h3>History</h3>
<p>The OpenSPARC project was launched by Sun Microsystems in 2006, releasing the UltraSPARC T1 and T2 processor designs as open-source hardware. The accompanying software — simulators, verification suites, and firmware — was released under the GPL. However, parts of the codebase originated from AT&T Unix source code, creating licensing uncertainty that prevented widespread adoption by the open-source community.</p>
<p>ReviveSparc was started in early 2026 to address this. By rebuilding everything from the published ISA specification — without reference to the original source code — we provide a legally clean, fully open-source implementation.</p>
<h3>Clean Room Process</h3>
<p>We follow a strict clean-room methodology:</p>
<ul>
<li>Developers working on the implementation have <strong>no access</strong> to the original OpenSPARC source code.</li>
<li>Only publicly available specification documents are used: the SPARC Architecture Manual v9, the UltraSPARC T1 Supplement, and the OpenSPARC specification.</li>
<li>All new code is written from scratch, with no derived or translated code from the original project.</li>
<li>The resulting code is licensed under the BSD 2-Clause License, permitting both open-source and proprietary use.</li>
</ul>
<h3>Project Goals</h3>
<ul>
<li><strong>Full SPARC V9 ISA compliance</strong> — user and privileged instructions, including VIS (Visual Instruction Set) extensions.</li>
<li><strong>Multi-core simulation</strong> — support for chip-multithreading (CMT) as in the original T1/T2 designs.</li>
<li><strong>Boot real operating systems</strong> — Linux, NetBSD, OpenBSD, and potentially Solaris.</li>
<li><strong>Hardware implementation path</strong> — provide a Verilog RTL target for FPGA prototyping.</li>
<li><strong>Educational resource</strong> — serve as a clean reference for students and researchers studying processor architecture.</li>
</ul>
<h3>Architecture Overview</h3>
<p>ReviveSparc targets the UltraSPARC architecture profile:</p>
<table>
<tr><th>Feature</th><th>Description</th></tr>
<tr><td>ISA</td><td>SPARC V9 (with VIS 1/2 extensions)</td></tr>
<tr><td>Pipeline</td><td>6-stage, in-order, dual-issue</td></tr>
<tr><td>Threading</td><td>4 threads per core (fine-grained CMT)</td></tr>
<tr><td>Cores</td><td>1 to 8</td></tr>
<tr><td>MMU</td><td>SPARC Reference MMU with TLB</td></tr>
<tr><td>Cache</td><td>Split I/D L1, unified L2</td></tr>
<tr><td>Interrupts</td><td>UltraSPARC-style interrupt controller</td></tr>
</table>
<h3>Repository Structure</h3>
<pre>revivesparc/
emu/ -- Functional instruction-set simulator
rtl/ -- Verilog RTL for synthesis
soft/ -- Firmware and boot ROM code
tests/ -- ISA verification test suite
tools/ -- Helper scripts and utilities
docs/ -- Additional documentation</pre>
</div>
<div id="footer">
<p>ReviveSparc is released under the BSD 2-Clause License.</p>
</div>
</body>
</html>
community.html
+129
View File
@@ -0,0 +1,129 @@
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>Community - ReviveSparc</title>
<link rel="stylesheet" href="style.css">
</head>
<body>
<div id="header">
<div class="inner">
<h1><a href="index.html">ReviveSparc</a></h1>
<p class="subtitle">An open-source OpenSPARC ISA reimplementation</p>
</div>
</div>
<div id="nav">
<div class="inner">
<ul>
<li><a href="index.html">Home</a></li>
<li><a href="about.html">About</a></li>
<li><a href="download.html">Download</a></li>
<li><a href="docs.html">Docs</a></li>
<li><a href="news.html">News</a></li>
<li><a href="roadmap.html">Roadmap</a></li>
<li><a href="screenshots.html">Screenshots</a></li>
<li><a href="community.html" class="active">Community</a></li>
<li><a href="sponsors.html">Sponsors</a></li>
</ul>
</div>
</div>
<div id="main">
<h2>Community</h2>
<p>ReviveSparc is a community-driven project. We welcome contributions, bug reports, and discussion from anyone interested in the SPARC architecture.</p>
<h3>Get Involved</h3>
<table>
<tr><th>Resource</th><th>Description</th><th>Link</th></tr>
<tr>
<td>GitHub</td>
<td>Source code, issue tracker, pull requests</td>
<td><a href="https://github.com/revivesparc">github.com/revivesparc</a></td>
</tr>
<tr>
<td>Mailing List</td>
<td>General discussion and development</td>
<td><a href="mailto:dev@revivesparc.org">dev@revivesparc.org</a></td>
</tr>
<tr>
<td>IRC</td>
<td>Real-time chat on Libera.Chat</td>
<td><a href="ircs://irc.libera.chat:6697/#revivesparc">#revivesparc</a></td>
</tr>
<tr>
<td>Discourse</td>
<td>Community forum for long-form discussion</td>
<td><a href="https://forum.revivesparc.org">forum.revivesparc.org</a></td>
</tr>
<tr>
<td>Wiki</td>
<td>Community-contributed guides and resources</td>
<td><a href="https://wiki.revivesparc.org">wiki.revivesparc.org</a></td>
</tr>
<tr>
<td>Bug Tracker</td>
<td>Report issues and feature requests</td>
<td><a href="https://github.com/revivesparc/revivesparc/issues">GitHub Issues</a></td>
</tr>
</table>
<h3>Contributing</h3>
<p>We welcome contributions of all kinds: code, documentation, testing, and hardware verification.</p>
<h4>Code Contributions</h4>
<ol>
<li>Fork the repository on GitHub.</li>
<li>Create a feature branch: <code>git checkout -b my-feature</code></li>
<li>Make your changes and add tests.</li>
<li>Run the test suite: <code>make test</code></li>
<li>Submit a pull request with a clear description of your changes.</li>
</ol>
<p>Before starting significant work, please post to the mailing list or open a discussion on GitHub to coordinate with other developers.</p>
<h4>Reporting Bugs</h4>
<p>When reporting a bug, please include:</p>
<ul>
<li>Your operating system and compiler version</li>
<li>The version of ReviveSparc (commit hash or release tag)</li>
<li>A minimal test case that reproduces the issue</li>
<li>The expected behavior and the actual behavior</li>
</ul>
<h3>Mailing List</h3>
<p>To subscribe to the ReviveSparc development mailing list, send an email to:</p>
<pre>dev+subscribe@revivesparc.org</pre>
<p>Archives are available at <a href="https://lists.revivesparc.org">lists.revivesparc.org</a>.</p>
<h3>License</h3>
<p>ReviveSparc is released under the <strong>BSD 2-Clause License</strong>:</p>
<pre>Copyright 2026 The ReviveSparc Project
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED.</pre>
</div>
<div id="footer">
<p>ReviveSparc is released under the BSD 2-Clause License.</p>
</div>
</body>
</html>
docs.html
+1375
View File
File diff suppressed because it is too large Load Diff
docs/api-reference.md
+187
View File
@@ -0,0 +1,187 @@
# API Reference
ReviveSparc provides a C API for embedding the SPARC emulator in other projects.
## Core API
### Initialization
```c
#include <revivesparc.h>
// Create a new SPARC CPU instance
sparc_t *sparc_new(sparc_isa_t isa);
```
Parameters:
- `isa`: `SPARC_V9` for 64-bit mode, `SPARC_V8` for 32-bit compatibility mode
Returns: Pointer to a new SPARC instance, or NULL on failure.
```c
// Create with custom configuration
sparc_t *sparc_new_with_config(const sparc_config_t *config);
```
```c
// Free a SPARC instance
void sparc_free(sparc_t *cpu);
```
### Loading Programs
```c
// Load an ELF file into memory
int sparc_load_elf(sparc_t *cpu, const char *path);
// Load a flat binary into memory at a specific address
int sparc_load_binary(sparc_t *cpu, const char *path, uint64_t addr);
// Load a file into memory at a specific offset
int sparc_load_file(sparc_t *cpu, const char *path, uint64_t addr);
```
All load functions return 0 on success, -1 on error.
### Execution Control
```c
// Reset the CPU to initial state
void sparc_reset(sparc_t *cpu);
// Run for a specified number of instructions
uint64_t sparc_run(sparc_t *cpu, uint64_t num_insts);
// Run until a breakpoint is hit
uint64_t sparc_run_until_break(sparc_t *cpu);
// Step a single instruction
int sparc_step(sparc_t *cpu);
// Stop execution (called from interrupt handler)
void sparc_stop(sparc_t *cpu);
```
Returns the actual number of instructions executed.
### Register Access
```c
// Read/write general-purpose registers
uint64_t sparc_get_gpr(sparc_t *cpu, int reg);
void sparc_set_gpr(sparc_t *cpu, int reg, uint64_t val);
// Read/write special registers
uint64_t sparc_get_pc(sparc_t *cpu);
void sparc_set_pc(sparc_t *cpu, uint64_t val);
uint64_t sparc_get_npc(sparc_t *cpu);
void sparc_set_npc(sparc_t *cpu, uint64_t val);
// Floating-point registers
double sparc_get_fpr(sparc_t *cpu, int reg);
void sparc_set_fpr(sparc_t *cpu, int reg, double val);
// Privileged registers
uint64_t sparc_get_priv(sparc_t *cpu, sparc_priv_reg_t reg);
void sparc_set_priv(sparc_t *cpu, sparc_priv_reg_t reg, uint64_t val);
```
### Memory Access
```c
// Direct memory access (bypasses MMU)
int sparc_mem_write(sparc_t *cpu, uint64_t addr, const void *buf, size_t len);
int sparc_mem_read(sparc_t *cpu, uint64_t addr, void *buf, size_t len);
// Virtual memory access (through MMU)
int sparc_virt_write(sparc_t *cpu, uint64_t addr, const void *buf, size_t len);
int sparc_virt_read(sparc_t *cpu, uint64_t addr, void *buf, size_t len);
```
Returns the number of bytes read/written, or -1 on error.
### Debugging
```c
// Set a breakpoint at a virtual address
int sparc_breakpoint_set(sparc_t *cpu, uint64_t addr);
// Clear a breakpoint
int sparc_breakpoint_clear(sparc_t *cpu, uint64_t addr);
// Get disassembly of an instruction
const char *sparc_disassemble(sparc_t *cpu, uint64_t addr);
// Set tracing level
void sparc_set_trace(sparc_t *cpu, int level);
```
## Configuration Structures
```c
typedef struct {
int num_cores; // Number of cores (1-8)
int threads_per_core; // Threads per core (1-4)
sparc_mem_t memory_model; // TSO, PSO, or RMO
sparc_sched_t sched_mode; // Fine or coarse-grained
uint64_t mem_size; // Main memory size in bytes
int l1i_size; // L1 I-cache size in bytes
int l1d_size; // L1 D-cache size in bytes
int l2_size; // L2 cache size in bytes
int num_windows; // Number of register windows (8-32)
} sparc_config_t;
```
## Error Handling
Most functions return 0 on success and -1 on error. Detailed error information can be retrieved:
```c
// Get the last error message
const char *sparc_error(sparc_t *cpu);
// Get the last error code
int sparc_errno(sparc_t *cpu);
```
## Example: Embedded Emulator
```c
#include <stdio.h>
#include <revivesparc.h>
int main(int argc, char **argv) {
sparc_t *cpu = sparc_new(SPARC_V9);
if (!cpu) {
fprintf(stderr, "Failed to create CPU\n");
return 1;
}
sparc_config_t config = {
.num_cores = 1,
.mem_size = 256 * 1024 * 1024,
.memory_model = MEM_TSO
};
sparc_configure(cpu, &config);
if (sparc_load_elf(cpu, argv[1]) != 0) {
fprintf(stderr, "Failed to load ELF: %s\n", sparc_error(cpu));
return 1;
}
sparc_reset(cpu);
uint64_t insts = sparc_run(cpu, 1000000);
printf("Executed %lu instructions\n", insts);
printf("Final PC: 0x%lx\n", sparc_get_pc(cpu));
sparc_free(cpu);
return 0;
}
```
Compile with:
```bash
cc -o myemu myemu.c -lrevivesparc
```
docs/build-guide.md
+146
View File
@@ -0,0 +1,146 @@
# Build Guide
Detailed build instructions for ReviveSparc across different platforms and configurations.
## Directory Structure
```
revivesparc/
emu/ -- Functional instruction-set simulator (C)
rtl/ -- Verilog RTL for synthesis
soft/ -- Firmware and boot ROM code
tests/ -- ISA verification test suite
tools/ -- Helper scripts and utilities
docs/ -- Additional documentation
Makefile -- Top-level build file
CMakeLists.txt -- CMake build configuration
```
## Build System
ReviveSparc supports two build systems: **Make** (simple) and **CMake** (advanced).
### Make (Default)
```bash
make
```
### CMake
```bash
mkdir build && cd build
cmake ..
make -j$(nproc)
```
CMake offers more granular control:
```bash
cmake .. -DCMAKE_BUILD_TYPE=Debug -DENABLE_TRACE=ON
```
## Platform-Specific Notes
### Linux (x86_64)
Standard build with GCC:
```bash
sudo apt install build-essential cmake git
git clone https://github.com/revivesparc/revivesparc.git
cd revivesparc
make
```
### Linux (aarch64)
```bash
sudo apt install build-essential cmake git
make
```
No additional steps required.
### macOS (Apple Silicon)
Install dependencies via Homebrew:
```bash
brew install cmake make gcc
make CC=gcc-14
```
### macOS (Intel)
```bash
brew install cmake make
make
```
## Cross-Compilation
To build for a different target architecture:
```bash
make CROSS=aarch64-linux-gnu-
```
This is useful for embedded ReviveSparc deployments.
## Building the RTL
The Verilog RTL requires Verilator or Icarus Verilog for simulation:
```bash
make rtl
```
For synthesis, see the [RTL Synthesis Guide](rtl-synthesis.md).
## Building the Toolchain
ReviveSparc includes scripts to build a complete SPARC cross-toolchain:
```bash
cd tools
./build-toolchain.sh
```
This builds `sparc-elf-gcc`, `sparc-linux-gcc`, and associated binutils. The toolchain is installed to `tools/toolchain/`.
## Common Build Issues
### "No such file or directory" for standard headers
Install libc development headers:
```bash
# Debian/Ubuntu
sudo apt install libc6-dev
# Fedora
sudo dnf install glibc-devel
# macOS
# Headers are included with Xcode Command Line Tools
```
### "cc1: error: unrecognized command-line option"
You may be using an older GCC. ReviveSparc requires GCC 8+ or Clang 10+.
### "undefined reference to `clock_gettime'"
Link with librt on older glibc versions:
```bash
make LDFLAGS=-lrt
```
## Cleaning the Build
```bash
make clean # Remove build artifacts
make distclean # Also remove generated files
```
docs/cmt.md
+106
View File
@@ -0,0 +1,106 @@
# Chip Multi-Threading (CMT)
ReviveSparc implements the UltraSPARC T1/T2 chip multi-threading architecture, allowing multiple threads to execute concurrently on each core.
## Architecture
```
Core 0 Core 1 Core 2 Core 3
+--------+ +--------+ +--------+ +--------+
| T0 T1 | | T0 T1 | | T0 T1 | | T0 T1 |
| T2 T3 | | T2 T3 | | T2 T3 | | T2 T3 |
+--------+ +--------+ +--------+ +--------+
| | | |
+--------------+--------------+--------------+
|
+-----------+
| L2 Cache |
+-----------+
```
Each core supports up to **4 hardware threads** with fine-grained interleaving. The pipeline switches between threads every cycle, hiding memory latency and maximizing throughput.
## Thread Scheduling
Threads are scheduled using a round-robin policy with two modes:
### Fine-Grained (Default)
The pipeline switches to a different thread each cycle. If the selected thread is stalled (cache miss, long latency operation), the pipeline switches to the next ready thread.
```c
// Pseudocode for thread selection
while (true) {
for (int i = 0; i < NUM_THREADS; i++) {
thread = (current_thread + i) % NUM_THREADS;
if (thread_is_ready(thread)) {
execute(thread);
break;
}
}
current_thread = (current_thread + 1) % NUM_THREADS;
}
```
### Coarse-Grained
Each thread runs for a fixed quantum (configurable, default 64 cycles) before yielding the pipeline. Useful for workloads with good instruction-level parallelism.
## Thread State
Each thread has its own fully replicated architectural state:
- **Register window** (16 registers, with window pointer)
- **PC and NPC** (program counters)
- **PSTATE** (processor state register)
- **TL** (trap level, up to 4)
- **Interrupt state** (pending interrupts, PIL)
## Memory Model
The T1/T2 memory model is **Total Store Order (TSO)** with per-thread write buffers. ReviveSparc implements:
- **TSO** by default (SPARC V9 default)
- **Partial Store Order (PSO)** as an alternative
- **Relaxed Memory Order (RMO)** for maximum performance
### Memory Barrier Instructions
| Instruction | Description |
|-------------|-------------|
| `MEMBAR #Sync` | Full memory barrier |
| `MEMBAR #StoreLoad` | Store before Load ordering |
| `MEMBAR #StoreStore` | Store before Store ordering |
| `MEMBAR #LoadLoad` | Load before Load ordering |
| `MEMBAR #LoadStore` | Load before Store ordering |
| `MEMBAR #Lookaside` | Invalidate lookaside buffers |
## Configuration
CMT parameters are configured at core initialization:
```c
sparc_core_config_t config = {
.num_threads = 4,
.sched_mode = SCHED_FINE_GRAINED,
.pipeline_mode = TSO,
.quantum = 64 // coarse-grained quantum
};
sparc_core_t *core = sparc_core_new(&config);
```
Or via command line:
```bash
./sparc-emu -cores 4 -threads 4 -sched fine kernel.bin
```
## Performance Considerations
- Fine-grained threading works best with high cache-miss rates (database, web serving)
- Coarse-grained threading works best with compute-intensive workloads
- The optimal thread count depends on the L2 cache size and memory latency
- Monitor thread utilization with the `-stats` flag:
```bash
./sparc-emu -stats kernel.bin
```
docs/faq.md
+107
View File
@@ -0,0 +1,107 @@
# Frequently Asked Questions
## General
### What is ReviveSparc?
ReviveSparc is a clean-room reimplementation of the OpenSPARC ISA (instruction set architecture). It aims to provide a fully open-source, legally unencumbered implementation of the SPARC V9 architecture that can run operating systems and software.
### Is this affiliated with Oracle?
No. ReviveSparc is an independent open-source project. OpenSPARC and SPARC are trademarks of Oracle Corporation. We are not affiliated with or endorsed by Oracle.
### Why SPARC? Isn't it dead?
SPARC is still used in mission-critical systems, particularly in aerospace, defense, and high-reliability computing. The Fujitsu SPARC64 processors power Japan's Fugaku supercomputer. The architecture is elegant and well-documented, making it ideal for educational use. ReviveSparc aims to preserve the architecture for future generations.
## Technical
### What is the "clean room" process?
Developers implementing ReviveSparc have **no access** to the original OpenSPARC source code. We work exclusively from publicly available specification documents:
- SPARC Architecture Manual Version 9
- UltraSPARC T1/T2 Supplements
- VIS Instruction Set Manual
This ensures the code is entirely original and free from any AT&T licensing concerns that affected the original OpenSPARC codebase.
### What operating systems can run?
- **Linux** (6.x series, full support)
- **NetBSD** (10.x, full support)
- **OpenBSD** (7.x, in progress)
- **Bare-metal programs** (any ELF binary for SPARC V9)
### How fast is the emulator?
On a modern x86_64 system:
- Single-core, JIT disabled: ~50 MIPS
- Single-core, JIT enabled: ~200 MIPS
- 8-core, JIT enabled: ~800 MIPS aggregate
Performance is sufficient to boot Linux in a few seconds.
### Can I synthesize the RTL on an FPGA?
Yes. The Verilog RTL has been tested on:
- Xilinx Virtex-7 (XC7VX485T) — 4 cores at 50 MHz
- Xilinx Kintex-7 (XC7K325T) — 2 cores at 75 MHz
- Intel Arria 10 — 4 cores at 100 MHz
See the [RTL Synthesis Guide](rtl-synthesis.md) for details.
## Project
### How can I contribute?
See the [Community page](../community.html) for details. We welcome code contributions, documentation, testing, and hardware verification.
### What license is used?
BSD 2-Clause License. This permits both open-source and proprietary use, with minimal restrictions.
### Does ReviveSparc include any AT&T code?
No. ReviveSparc is a complete from-scratch reimplementation. Every line of code is original and written solely from the architecture specification.
### Are there plans for SPARC V8 (32-bit) support?
The emulator includes a SPARC V8 compatibility mode that handles 32-bit code. Pure 32-bit SPARC V8 is not a primary target, but the majority of V8 instructions are supported through the V9 backward compatibility features.
### Can I run Solaris?
Solaris 10 and Solaris 11 for SPARC are not currently supported. The primary targets are open-source operating systems. If you'd like to contribute Solaris support, please reach out on the mailing list.
### Why not just use QEMU's SPARC target?
QEMU's SPARC target is excellent for running SPARC binaries, but it is a functional emulator with less emphasis on:
- Cycle-accurate pipeline modeling
- Hardware synthesis targets
- Educational clarity
ReviveSparc complements QEMU by providing a reference implementation suitable for hardware design and teaching.
## Build Issues
### `make` fails with "undefined reference"
Ensure you have all dependencies installed. See the [Build Guide](build-guide.md) for your platform.
### The emulator crashes on startup
Run with debug output enabled:
```bash
./sparc-emu -d -v kernel.bin
```
This will show detailed trace information. File a bug report with the output.
### Linux kernel hangs during boot
Common causes:
- Missing or incorrect device tree blob (use the DTB from `revivesparc.dtb`)
- Incorrect kernel command-line parameters
- Kernel built without ReviveSparc platform support
Try booting with `-append "earlyprintk debug"` to see kernel messages.
docs/getting-started.md
+105
View File
@@ -0,0 +1,105 @@
# Getting Started with ReviveSparc
This guide will walk you through building ReviveSparc from source and running your first SPARC program.
## Prerequisites
- **Linux** (x86_64 or aarch64) or **macOS** (Intel or Apple Silicon)
- **GCC** or **Clang** (C11 support required)
- **Make** (3.81 or later)
- **CMake** (3.20 or later)
- **Git**
Optional but recommended:
- `gcc-sparc-linux-gnu` for cross-compiling SPARC Linux programs
- `qemu-system-sparc64` for comparison testing
## Building from Source
Clone the repository:
```bash
git clone https://github.com/revivesparc/revivesparc.git
cd revivesparc
```
Build the emulator:
```bash
make
```
The resulting binary is `sparc-emu` in the project root directory.
### Build Options
| Option | Description | Default |
|--------|-------------|---------|
| `DEBUG=1` | Enable debug symbols and verbose logging | off |
| `OPT=0` | Disable optimizations | off |
| `TRACE=1` | Enable instruction tracing | off |
| `CC=clang` | Use Clang instead of GCC | gcc |
Example with debug enabled:
```bash
make DEBUG=1
```
## Running the Test Suite
```bash
make test
```
This runs the ISA verification suite, which tests every implemented instruction against known-good results.
## Your First SPARC Program
Create a file `hello.S` with the following SPARC assembly:
```asm
.section ".text"
.global _start
_start:
save %sp, -96, %sp
mov 1, %g1 ! SYS_write
mov 1, %o0 ! fd = stdout
sethi %hi(msg), %o1
or %o1, %lo(msg), %o1
mov 13, %o2 ! length
ta 0x6d ! trap to kernel
clr %o0 ! status = 0
mov 1, %g1 ! SYS_exit
ta 0x6d
.section ".data"
msg:
.asciz "Hello, SPARC!\n"
```
Assemble and link using the SPARC cross-toolchain:
```bash
sparc-linux-as hello.S -o hello.o
sparc-linux-ld hello.o -o hello
```
Run it under ReviveSparc:
```bash
./sparc-emu hello
```
You should see:
```
Hello, SPARC!
```
## Next Steps
- Read the [Build Guide](build-guide.md) for advanced build configurations
- Explore the [ISA Reference](isa-reference.md) for instruction set details
- Check the [FAQ](faq.md) for common questions
docs/isa-reference.md
+137
View File
@@ -0,0 +1,137 @@
# SPARC V9 ISA Reference
Reference documentation for the SPARC V9 instruction set as implemented in ReviveSparc.
## Overview
The SPARC V9 architecture is a 64-bit RISC ISA developed by Sun Microsystems and standardized by SPARC International. ReviveSparc implements the full SPARC V9 specification, including the VIS (Visual Instruction Set) extensions.
### Key Features
- 64-bit integer and floating-point registers
- 32 general-purpose registers (register windowed)
- 32 floating-point registers (quad-precision capable)
- Delayed branching with annulment
- Register windowing with 8 global + up to 32 windowed registers
- Precise exceptions and multiple trap levels
## Instruction Set Categories
### Integer Instructions
```
ADD Add ADDcc Add and modify CC
AND And ANDcc And and modify CC
OR Or ORcc Or and modify CC
XOR Exclusive Or XORcc Exclusive Or and modify CC
SUB Subtract SUBcc Subtract and modify CC
MULX Multiply Extended UDIVX Unsigned Divide Extended
SDIVX Signed Divide Extended
SLL Shift Left Logical SRL Shift Right Logical
SRA Shift Right Arithmetic
```
### Load/Store Instructions
```
LDUB Load Unsigned Byte
LDSB Load Signed Byte
LDUH Load Unsigned Halfword
LDSH Load Signed Halfword
LDW Load Word
LDX Load Doubleword
STB Store Byte
STH Store Halfword
STW Store Word
STX Store Doubleword
LDF Load Floating-point
LDDF Load Double Floating-point
STF Store Floating-point
STDF Store Double Floating-point
```
### Branch Instructions
```
Bcc Branch on Condition
BPcc Branch on Condition (Predicted)
BPr Branch on Register
CALL Call and Link
RETT Return from Trap
JMPL Jump and Link
RETURN Return from Subroutine
```
### Floating-Point Instructions
```
FADDs FP Add (single)
FADDd FP Add (double)
FSUBs FP Subtract (single)
FSUBd FP Subtract (double)
FMULs FP Multiply (single)
FMULd FP Multiply (double)
FDIVs FP Divide (single)
FDIVd FP Divide (double)
FSQRTs FP Square Root (single)
FSQRTd FP Square Root (double)
F CMPs FP Compare (single)
F CMPd FP Compare (double)
```
### VIS Instructions
```
FPACK16 Pack 16-bit
FPACK32 Pack 32-bit
FALIGNDATA Align Data
FEXPAND Expand
FMUL8x16 Multiply 8-bit by 16-bit
FMUL8x16AU Multiply 8-bit by 16-bit (unsigned)
FMUL8x16AL Multiply 8-bit by 16-bit (unsigned)
FMUL8SUx16 Multiply 8-bit Signed by 16-bit Unsigned
FMUL8ULx16 Multiply 8-bit Unsigned by 16-bit Unsigned
FMULD8SUx16 Multiply Double 8-bit Signed by 16-bit Unsigned
FMULD8ULx16 Multiply Double 8-bit Unsigned by 16-bit Unsigned
```
## Register Windows
SPARC V9 uses register windows to optimize function call performance:
- **8 global registers** (%g0 through %g7, where %g0 is always zero)
- **Up to 32 register windows**, each containing 16 registers
- Each window provides: 8 incoming (%i0-%i7), 8 local (%l0-%l7), 8 outgoing (%o0-%o7) — with overlap between adjacent windows
- The number of windows is implementation-dependent
## Privileged Registers
| Register | Description |
|----------|-------------|
| TPC | Trap PC (1-4) |
| TNPC | Trap Next PC (1-4) |
| TSTATE | Trap State (1-4) |
| TT | Trap Type (1-4) |
| TBA | Trap Base Address |
| PSTATE | Processor State |
| TL | Trap Level |
| PIL | Processor Interrupt Level |
| CWP | Current Window Pointer |
| CANSAVE | Cleanable Windows |
| CANRESTORE | Restorable Windows |
## Trap Types
| TT Value | Trap Name | Description |
|----------|-----------|-------------|
| 0x01 | instruction_access_exception | Memory access fault |
| 0x03 | instruction_access_error | Hardware error |
| 0x04 | illegal_instruction | Unimplemented instruction |
| 0x05 | privileged_operation | Trap in user mode |
| 0x06 | fp_disabled | FPU not enabled |
| 0x08 | clean_window | Register window spill needed |
| 0x09 | division_by_zero | Integer divide by zero |
| 0x20-0x2f | interrupt_vector | External interrupts |
| 0x60-0x7f | software_trap | `ta` instruction traps |
| 0x80 | data_access_exception | Data memory access fault |
| 0x82 | data_access_error | Data memory hardware error |
docs/linux-guide.md
+154
View File
@@ -0,0 +1,154 @@
# Building Linux for ReviveSparc
This guide covers building and booting a Linux kernel on the ReviveSparc emulator.
## Supported Kernels
| Kernel Version | Status | Notes |
|----------------|--------|-------|
| 6.12+ | Full | All features working |
| 6.6 LTS | Full | Recommended for production |
| 6.1 LTS | Full | Older but stable |
| 5.15 LTS | Partial | No SMP support |
## Cross-Compilation Setup
Install a SPARC64 cross-compiler:
```bash
# Debian/Ubuntu
sudo apt install gcc-sparc64-linux-gnu
# Fedora
sudo dnf install cross-gcc-sparc64-linux-gnu
# Build from source (see toolchain guide)
./tools/build-toolchain.sh --target=sparc64-linux-gnu
```
## Building the Kernel
### Get the Source
```bash
git clone https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
cd linux
git checkout v6.12
```
### Apply ReviveSparc Patches
```bash
# From the ReviveSparc repository
./tools/apply-kernel-patches.sh /path/to/linux
```
### Configure
```bash
make ARCH=sparc64 CROSS_COMPILE=sparc64-linux-gnu- revivesparc_defconfig
```
Or customize:
```bash
make ARCH=sparc64 CROSS_COMPILE=sparc64-linux-gnu- menuconfig
```
### Build
```bash
make ARCH=sparc64 CROSS_COMPILE=sparc64-linux-gnu- -j$(nproc)
```
The kernel image is at `arch/sparc64/boot/image` and `vmlinux` (ELF).
## Building an Initramfs
Create a minimal root filesystem:
```bash
# Create a simple init script
cat > init << 'EOF'
#!/bin/busybox
/bin/busybox --install -s
mount -t proc proc /proc
mount -t sysfs sysfs /sys
echo "Welcome to ReviveSparc Linux!"
exec /bin/sh
EOF
# Create the initramfs
mkdir -p rootfs/{bin,proc,sys,dev,etc}
cp init rootfs/
cp /path/to/busybox rootfs/bin/
# Package it
cd rootfs
find . | cpio -H newc -o | gzip > ../initramfs.gz
```
## Booting
```bash
./sparc-emu \
-kernel vmlinux \
-initrd initramfs.gz \
-append "console=ttyS0,115200 root=/dev/ram rdinit=/init" \
-nographic
```
### Command-Line Options
| Option | Description |
|--------|-------------|
| `-kernel` | Path to the kernel vmlinux |
| `-initrd` | Path to the initramfs image |
| `-append` | Kernel command line |
| `-nographic` | No graphical output (serial console) |
| `-m` | Memory size (e.g., `-m 512M`) |
| `-smp` | Number of cores (e.g., `-smp 4`) |
| `-net` | Network backend (e.g., `-net user`) |
### Booting with Device Tree
ReviveSparc provides a device tree blob (DTB) for the emulated platform:
```bash
./sparc-emu \
-kernel vmlinux \
-dtb revivesparc.dtb \
-initrd initramfs.gz \
-append "console=ttyS0,115200" \
-nographic
```
## Building for NetBSD
```bash
# Build a SPARC64 NetBSD kernel
cd /usr/src
./build.sh -m sparc64 -U kernel=GENERIC
# Run under ReviveSparc
./sparc-emu \
-kernel netbsd-sparc64 \
-append "console=com0" \
-nographic
```
## Building for OpenBSD
```bash
# Build a SPARC64 OpenBSD kernel
cd /usr/src
make -C sys/arch/sparc64/conf GENERIC
config GENERIC
cd ../compile/GENERIC
make
# Run under ReviveSparc
./sparc-emu \
-kernel bsd.sparc64 \
-nographic
```
docs/memory-model.md
+134
View File
@@ -0,0 +1,134 @@
# Memory Model
ReviveSparc implements the SPARC V9 memory architecture, including the cache hierarchy, MMU, and memory ordering models.
## Cache Hierarchy
```
CLIENT (Core)
|
+-- L1 I-Cache (16 KB, 4-way, 32-byte line)
+-- L1 D-Cache (16 KB, 4-way, 32-byte line)
|
+-- L2 Cache (shared, 512 KB - 4 MB, 8-way)
|
+-- Main Memory (DDR4, configurable)
```
### L1 Caches
- **Capacity**: 16 KB each for instructions and data
- **Associativity**: 4-way set associative
- **Line size**: 32 bytes
- **Latency**: 2 cycles (hit), 1 cycle (tag check)
- **Policy**: Write-back (D-cache), read-only (I-cache)
- **Coherency**: MOESI protocol between cores
### L2 Cache
- **Capacity**: Configurable (512 KB to 4 MB)
- **Associativity**: 8-way set associative
- **Line size**: 64 bytes
- **Latency**: 12 cycles (hit)
- **Policy**: Write-back, write-allocate
- **Coherency**: Inclusive of L1 (snoop filter)
## MMU (Memory Management Unit)
The SPARC Reference MMU provides virtual-to-physical address translation.
### Address Spaces
| Mode | Virtual Address Width | Physical Address Width |
|------|----------------------|----------------------|
| 32-bit (V8 compat) | 32 bits | 40 bits |
| 64-bit (V9) | 44 bits | 44 bits |
### TLB Structure
```
ITLB (64 entries)
Fully associative
Supports 8 KB, 64 KB, 256 KB, 4 MB pages
DTLB (64 entries)
Fully associative
Supports same page sizes as ITLB
```
### Translation Process
```
Virtual Address (44 bits)
|
+-- VPN[0:2] --> TLB Lookup (parallel)
| |
| +-- Hit? --> PPN + Offset --> Physical Address
| +-- Miss --> TLB Miss Trap (TLB miss handler)
|
+-- Offset --> Direct to physical address
```
### TSB (Translation Storage Buffer)
The TSB is a software-managed cache of page table entries. On a TLB miss, the trap handler searches the TSB before walking the full page table.
## Memory Ordering
ReviveSparc supports three memory models:
### Total Store Order (TSO)
The default SPARC V9 model:
- Stores appear in program order to all observers
- Loads may pass stores (store buffer forwarding)
- Atomic operations provide full ordering
### Partial Store Order (PSO)
Relaxed store ordering:
- Stores to different locations may be reordered
- Stores to the same location appear in order
- MEMBAR is required for ordering constraints
### Relaxed Memory Order (RMO)
Maximum relaxation:
- Loads and stores may be reordered freely
- All ordering is explicit via MEMBAR instructions
- Highest performance on multi-core configurations
## Atomic Operations
| Instruction | Description |
|-------------|-------------|
| `CAS` | Compare and Swap (32-bit) |
| `CASX` | Compare and Swap (64-bit) |
| `SWAP` | Atomic swap |
| `LDSTUB` | Atomic load-and-store-byte |
| `CASA` | Compare and Swap (alternate space) |
| `CASXA` | Compare and Swap (alternate space, 64-bit) |
## Configuration
Memory parameters can be configured at startup:
```bash
./sparc-emu -l1i 16k -l1d 16k -l2 1m -mem tso kernel.bin
```
Or via the C API:
```c
sparc_mem_config_t mem = {
.l1i_size = 16 * 1024,
.l1d_size = 16 * 1024,
.l2_size = 1 * 1024 * 1024,
.memory_model = MEM_TSO,
.num_cores = 4
};
sparc_t *cpu = sparc_new_with_config(&mem);
```
docs/rtl-synthesis.md
+115
View File
@@ -0,0 +1,115 @@
# RTL Synthesis Guide
This guide covers synthesizing the ReviveSparc Verilog RTL for FPGA deployment.
## Overview
The ReviveSparc RTL implements a 6-stage, in-order, dual-issue SPARC V9 pipeline with chip multi-threading. It is written in synthesizable Verilog and targets Xilinx and Intel FPGAs.
## Pipeline Stages
```
Fetch --> Decode --> Execute --> Memory --> Writeback --> Commit
| | | | | |
v v v v v v
ICache Decode ALU/MUL D-Cache RegFile TLB/MMU
```
## Prerequisites
- **Verilator** 5.x (for simulation)
- **Vivado** 2024.x or **Quartus** 23.x (for synthesis)
- **Python** 3.10+ (for build scripts)
- **FuseSoC** (optional, for IP management)
## Building the RTL Simulation
```bash
make rtl
```
This compiles the RTL with Verilator and produces a simulation binary.
### Running RTL Tests
```bash
make rtl-test
```
This runs the complete RTL test suite, including unit tests for each pipeline stage and integration tests for the full core.
## FPGA Synthesis
### Xilinx Vivado
```bash
cd rtl/syn/vivado
vivado -mode batch -source synth.tcl
```
This generates a bitstream for the default target board.
### Target Boards
| Board | Speed | Resources Used | Status |
|-------|-------|----------------|--------|
| Xilinx VC707 (Virtex-7) | 50 MHz, 4 cores | 65% LUT, 48% BRAM | Verified |
| Xilinx KC705 (Kintex-7) | 75 MHz, 2 cores | 55% LUT, 35% BRAM | Verified |
| Xilinx Arty A7 (Artix-7) | 40 MHz, 1 core | 70% LUT, 60% BRAM | Verified |
| Intel Arria 10 GX | 100 MHz, 4 cores | 60% ALM, 40% M20K | Verified |
| Intel Cyclone V | 50 MHz, 2 cores | 72% ALM, 55% M20K | Beta |
### Configuration
RTL parameters are set in `rtl/config.vh`:
```verilog
`define NUM_CORES 4
`define THREADS_PER_CORE 4
`define L1I_SIZE 16384
`define L1D_SIZE 16384
`define L2_SIZE 1048576
`define PIPELINE_STAGES 6
```
## Running on FPGA
1. Program the FPGA with the generated bitstream
2. Connect a USB-UART cable (default: 115200 baud, 8N1)
3. Load a program via the boot ROM interface:
```bash
./tools/fpga-load.py /dev/ttyUSB0 kernel.bin
```
4. The core resets and begins execution. Output appears on the serial console.
## Boot ROM
The boot ROM loads a program from the UART interface into memory and starts execution at the entry point. The boot ROM firmware is in `soft/bootrom/` and is pre-synthesized into the bitstream.
## Debug Interface
The RTL includes a JTAG-like debug interface accessible via the emulator:
```bash
./sparc-emu --connect-fpga /dev/ttyUSB1
```
This connects the emulator's debugger to the FPGA-resident cores, allowing register inspection and breakpoint management.
## Performance Results
| Configuration | FPGA | Frequency | DMIPS |
|---------------|------|-----------|-------|
| 1 core, 4 threads | Artix-7 | 40 MHz | 45 |
| 2 cores, 4 threads | Kintex-7 | 75 MHz | 168 |
| 4 cores, 4 threads | Virtex-7 | 50 MHz | 320 |
| 4 cores, 4 threads | Arria 10 | 100 MHz | 720 |
## Contributing RTL Changes
1. Write a Verilog testbench in `rtl/tb/`
2. Verify with Verilator: `make rtl-test`
3. Ensure lint passes: `make rtl-lint`
4. Submit a pull request with simulation results
download.html
+104
View File
@@ -0,0 +1,104 @@
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>Download - ReviveSparc</title>
<link rel="stylesheet" href="style.css">
</head>
<body>
<div id="header">
<div class="inner">
<h1><a href="index.html">ReviveSparc</a></h1>
<p class="subtitle">An open-source OpenSPARC ISA reimplementation</p>
</div>
</div>
<div id="nav">
<div class="inner">
<ul>
<li><a href="index.html">Home</a></li>
<li><a href="about.html">About</a></li>
<li><a href="download.html" class="active">Download</a></li>
<li><a href="docs.html">Docs</a></li>
<li><a href="news.html">News</a></li>
<li><a href="roadmap.html">Roadmap</a></li>
<li><a href="screenshots.html">Screenshots</a></li>
<li><a href="community.html">Community</a></li>
<li><a href="sponsors.html">Sponsors</a></li>
</ul>
</div>
</div>
<div id="main">
<h2>Download ReviveSparc</h2>
<h3>Source Code</h3>
<p>The ReviveSparc source repository is hosted on GitHub. Clone it with:</p>
<pre>git clone https://github.com/revivethesparc/revivesparc.git</pre>
<p>Or download a tarball of any release below.</p>
<h3>Releases</h3>
<table>
<tr><th>Version</th><th>Date</th><th>Description</th><th>Download</th></tr>
<tr>
<td>v0.4.0</td>
<td>2026-06-10</td>
<td>Full SPARC V9 user-space support. All integer and FP instructions implemented and verified.</td>
<td><a href="#">revivesparc-0.4.0.tar.gz</a></td>
</tr>
<tr>
<td>v0.3.0</td>
<td>2026-05-01</td>
<td>Privileged instruction support, MMU, and interrupt controller. Linux kernel boots to shell.</td>
<td><a href="#">revivesparc-0.3.0.tar.gz</a></td>
</tr>
<tr>
<td>v0.2.0</td>
<td>2026-03-15</td>
<td>Multi-core support, cache simulation, and VIS instruction set extensions.</td>
<td><a href="#">revivesparc-0.2.0.tar.gz</a></td>
</tr>
<tr>
<td>v0.1.0</td>
<td>2026-02-14</td>
<td>Initial release. Single-core user-space simulation with basic integer instruction set.</td>
<td><a href="#">revivesparc-0.1.0.tar.gz</a></td>
</tr>
</table>
<h3>Toolchain</h3>
<p>Pre-built cross-compilation toolchains for SPARC targets are available:</p>
<table>
<tr><th>Package</th><th>Description</th><th>Download</th></tr>
<tr><td>sparc-elf-gcc-14.2.0</td><td>Cross GCC targeting SPARC ELF (bare-metal)</td><td><a href="#">sparc-elf-gcc.tar.xz</a></td></tr>
<tr><td>sparc-linux-gcc-14.2.0</td><td>Cross GCC targeting SPARC Linux</td><td><a href="#">sparc-linux-gcc.tar.xz</a></td></tr>
<tr><td>sparc-binutils-2.43</td><td>Cross binutils for SPARC targets</td><td><a href="#">sparc-binutils.tar.xz</a></td></tr>
</table>
<h3>System Images</h3>
<table>
<tr><th>Image</th><th>Description</th><th>Download</th></tr>
<tr><td>revivesparc-linux-boot</td><td>Minimal Linux kernel + initramfs for ReviveSparc</td><td><a href="#">linux-boot.tar.gz</a></td></tr>
<tr><td>revivesparc-netbsd-boot</td><td>NetBSD 10.0 disk image for ReviveSparc</td><td><a href="#">netbsd-boot.tar.gz</a></td></tr>
</table>
<h3>Building from Source</h3>
<p>ReviveSparc builds on Linux and macOS. Required dependencies: <code>gcc</code> or <code>clang</code>, <code>make</code>, <code>cmake</code>.</p>
<pre>git clone https://github.com/revivethesparc/revivesparc.git
cd revivesparc
make
# Optional: run the test suite
make test</pre>
<p>See the <a href="docs.html">build documentation</a> for detailed instructions and platform-specific notes.</p>
</div>
<div id="footer">
<p>ReviveSparc is released under the BSD 2-Clause License.</p>
</div>
</body>
</html>
index.html
+95
View File
@@ -0,0 +1,95 @@
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>ReviveSparc - Bringing OpenSPARC Back</title>
<link rel="stylesheet" href="style.css">
</head>
<body>
<div id="header">
<div class="inner">
<h1><a href="index.html">ReviveSparc</a></h1>
<p class="subtitle">An open-source OpenSPARC ISA reimplementation</p>
</div>
</div>
<div id="nav">
<div class="inner">
<ul>
<li><a href="index.html" class="active">Home</a></li>
<li><a href="about.html">About</a></li>
<li><a href="download.html">Download</a></li>
<li><a href="docs.html">Docs</a></li>
<li><a href="news.html">News</a></li>
<li><a href="roadmap.html">Roadmap</a></li>
<li><a href="screenshots.html">Screenshots</a></li>
<li><a href="community.html">Community</a></li>
<li><a href="sponsors.html">Sponsors</a></li>
</ul>
</div>
</div>
<div id="main">
<div class="hero">
<h2>Revive the SPARC</h2>
<p>ReviveSparc is a clean-room reimplementation of the OpenSPARC ISA, aiming to bring the SPARC architecture back to life with a modern, open-source codebase. Free from legacy AT&T licensing concerns, built for the future.</p>
<a class="btn" href="download.html">Download Latest &rarr;</a>
</div>
<h2>What is ReviveSparc?</h2>
<p>ReviveSparc is a from-scratch reimplementation of the OpenSPARC T1/T2 instruction set architecture. The original OpenSPARC project by Sun Microsystems was released under the GPL, but contained AT&T-derived code that created licensing uncertainty. ReviveSparc replaces every line of that code with fresh, permissively-licensed implementations.</p>
<h2>Features</h2>
<div class="features">
<div class="feature">
<h3>Clean Room</h3>
<p>Every line of ReviveSparc is original code, written from the ISA specification. No AT&T heritage, no licensing grey areas.</p>
</div>
<div class="feature">
<h3>Multi-Core</h3>
<p>Supports up to 8 cores with fine-grained threading, mirroring the UltraSPARC T1/T2 design philosophy.</p>
</div>
<div class="feature">
<h3>Toolchain</h3>
<p>Includes a GCC port, binutils support, and a QEMU system-emulation target. Boot Linux, NetBSD, or OpenBSD.</p>
</div>
</div>
<h2>News</h2>
<div id="home-news">
<p class="meta">Loading...</p>
</div>
<p><a href="news.html">All news &amp; releases &rarr;</a></p>
<h2>Quick Start</h2>
<pre>git clone https://github.com/revivesparc/revivesparc.git
cd revivesparc
make
./sparc-emu -kernel vmlinux</pre>
<p>See the <a href="docs.html">documentation</a> for detailed build and usage instructions.</p>
</div>
<div id="footer">
<p>ReviveSparc is released under the BSD 2-Clause License.<br>
OpenSPARC is a registered trademark of Oracle Corporation. ReviveSparc is not affiliated with or endorsed by Oracle.</p>
</div>
<script type="text/json" id="home-news-data">[
{"date":"2026-06-15","title":"ReviveSparc Initial Development","body":"The project has officially started."}
]</script>
<script>
var entries = JSON.parse(document.getElementById("home-news-data").textContent);
var html = "";
entries.slice(0, 3).forEach(function (e) {
var snippet = e.title;
if (e.body) snippet += ' &mdash; ' + e.body.replace(/<[^>]+>/g, '').split('.')[0] + '.';
html += '<div class="news-item"><span class="date">' + e.date + '</span> &mdash; ' + snippet + '</div>';
});
document.getElementById("home-news").innerHTML = html;
</script>
</body>
</html>
news.html
+86
View File
@@ -0,0 +1,86 @@
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>News - ReviveSparc</title>
<link rel="stylesheet" href="style.css">
</head>
<body>
<div id="header">
<div class="inner">
<h1><a href="index.html">ReviveSparc</a></h1>
<p class="subtitle">An open-source OpenSPARC ISA reimplementation</p>
</div>
</div>
<div id="nav">
<div class="inner">
<ul>
<li><a href="index.html">Home</a></li>
<li><a href="about.html">About</a></li>
<li><a href="download.html">Download</a></li>
<li><a href="docs.html">Docs</a></li>
<li><a href="news.html" class="active">News</a></li>
<li><a href="roadmap.html">Roadmap</a></li>
<li><a href="screenshots.html">Screenshots</a></li>
<li><a href="community.html">Community</a></li>
<li><a href="sponsors.html">Sponsors</a></li>
</ul>
</div>
</div>
<div id="main">
<h2>News &amp; Releases</h2>
<div id="news-container">
<p class="meta">Loading...</p>
</div>
<h3>RSS Feed</h3>
<p>Subscribe to the <a href="#">RSS feed</a> for release announcements and project updates.</p>
</div>
<div id="footer">
<p>ReviveSparc is released under the BSD 2-Clause License.</p>
</div>
<script type="text/json" id="news-data">[
{
"date": "2026-06-15",
"title": "ReviveSparc Initial Development",
"body": "The project has officially started. We are currently in the research phase, working hard to make this work.",
"link": "index.html",
"linkText": "Read More"
}
]</script>
<script>
function renderNews() {
var container = document.getElementById("news-container");
var entries = JSON.parse(document.getElementById("news-data").textContent);
var html = "";
entries.forEach(function (e) {
html += '<div class="news-item">';
html += '<span class="date">' + e.date + '</span>';
html += '<h3>' + e.title + '</h3>';
html += '<p>' + e.body + '</p>';
if (e.items && e.items.length) {
html += '<ul>';
e.items.forEach(function (item) { html += '<li>' + item + '</li>'; });
html += '</ul>';
}
if (e.link) {
html += '<p><a href="' + e.link + '">' + (e.linkText || e.link) + '</a></p>';
}
html += '</div>';
});
container.innerHTML = html;
}
renderNews();
</script>
</body>
</html>
news.json
+9
View File
@@ -0,0 +1,9 @@
[
{
"date": "2026-06-15",
"title": "ReviveSparc Initial Development",
"body": "The project has officially started. We are currently in the research phase, working hard to make this work.",
"link": "index.html",
"linkText": "Read More"
}
]
roadmap.html
+96
View File
@@ -0,0 +1,96 @@
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>Roadmap - ReviveSparc</title>
<link rel="stylesheet" href="style.css">
</head>
<body>
<div id="header">
<div class="inner">
<h1><a href="index.html">ReviveSparc</a></h1>
<p class="subtitle">An open-source OpenSPARC ISA reimplementation</p>
</div>
</div>
<div id="nav">
<div class="inner">
<ul>
<li><a href="index.html">Home</a></li>
<li><a href="about.html">About</a></li>
<li><a href="download.html">Download</a></li>
<li><a href="docs.html">Docs</a></li>
<li><a href="news.html">News</a></li>
<li><a href="roadmap.html" class="active">Roadmap</a></li>
<li><a href="screenshots.html">Screenshots</a></li>
<li><a href="community.html">Community</a></li>
<li><a href="sponsors.html">Sponsors</a></li>
</ul>
</div>
</div>
<div id="main">
<h2>Roadmap</h2>
<p>This page outlines the planned development milestones for ReviveSparc. Timelines are approximate and depend on contributor availability.</p>
<div id="roadmap-container">
<p class="meta">Loading...</p>
</div>
</div>
<div id="footer">
<p>ReviveSparc is released under the BSD 2-Clause License.</p>
</div>
<script type="text/json" id="roadmap-data">{
"milestones": [
{
"version": "v0.0.1",
"title": "Initial structure",
"status": "planned",
"date": "Jun 2026",
"items": [
"Intial repository structure."
]
}
],
"future": [
"SPARC V9e extensions — VIS 3, integer multiply-add, SHA-3 instructions",
"Vector processing unit — SIMD engine inspired by SPARC64 VIIIfx",
"PCIe host bridge — Allow real hardware peripherals in emulation",
"GDB JTAG bridge — Connect GDB to FPGA-resident cores",
"WebAssembly backend — Run ReviveSparc in the browser"
]
}</script>
<script>
function renderRoadmap() {
var container = document.getElementById("roadmap-container");
var data = JSON.parse(document.getElementById("roadmap-data").textContent);
var html = "";
data.milestones.forEach(function (m) {
var statusClass = m.status === "released" ? "released" : "target";
var statusLabel = m.status === "released" ? "released" : "target: " + m.date;
html += '<h3>' + m.version + ' &mdash; ' + m.title + ' <span class="meta ' + statusClass + '">(' + statusLabel + ')</span></h3>';
html += '<ul>';
m.items.forEach(function (item) { html += '<li>' + item + '</li>'; });
html += '</ul>';
});
html += '<h3>Future Ideas</h3>';
html += '<ul>';
data.future.forEach(function (idea) { html += '<li>' + idea + '</li>'; });
html += '</ul>';
container.innerHTML = html;
}
renderRoadmap();
</script>
</body>
</html>
roadmap.json
+17
View File
@@ -0,0 +1,17 @@
{
"milestones": [
{
"version": "v0.4.0",
"title": "Full User-Space ISA",
"status": "released",
"date": "Jun 2026",
"items": [
"All SPARC V9 integer instructions implemented and verified",
"All floating-point instructions (single, double, quad precision)",
"VIS 1 and VIS 2 instruction set extensions",
"Register window management (spill/fill traps)",
"Comprehensive ISA test suite: ~12,000 test cases"
]
}
]
}
screenshots.html
+196
View File
@@ -0,0 +1,196 @@
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>Screenshots - ReviveSparc</title>
<link rel="stylesheet" href="style.css">
<style>
.screenshot {
border: 1px solid #ccc;
margin: 0 0 30px 0;
background: #f0f0e8;
}
.screenshot .preview {
background: #1a1a1a;
color: #00ff00;
font-family: "Lucida Console", Monaco, "Courier New", monospace;
font-size: 13px;
line-height: 1.4;
padding: 16px;
overflow-x: auto;
white-space: pre;
min-height: 120px;
}
.screenshot .caption {
padding: 10px 16px;
border-top: 1px solid #ccc;
font-size: 13px;
}
.screenshot .caption strong {
text-transform: uppercase;
letter-spacing: 1px;
}
</style>
</head>
<body>
<div id="header">
<div class="inner">
<h1><a href="index.html">ReviveSparc</a></h1>
<p class="subtitle">An open-source OpenSPARC ISA reimplementation</p>
</div>
</div>
<div id="nav">
<div class="inner">
<ul>
<li><a href="index.html">Home</a></li>
<li><a href="about.html">About</a></li>
<li><a href="download.html">Download</a></li>
<li><a href="docs.html">Docs</a></li>
<li><a href="news.html">News</a></li>
<li><a href="roadmap.html">Roadmap</a></li>
<li><a href="screenshots.html" class="active">Screenshots</a></li>
<li><a href="community.html">Community</a></li>
<li><a href="sponsors.html">Sponsors</a></li>
</ul>
</div>
</div>
<div id="main">
<h2>Screenshots</h2>
<p>Terminal captures of ReviveSparc in action.</p>
<div class="screenshot">
<div class="preview">ReviveSparc v0.4.0 — SPARC V9 Emulator
Copyright 2026 The ReviveSparc Project
License BSD-2-Clause
$ ./sparc-emu hello
[ReviveSparc] Loading ELF: hello
[ReviveSparc] Entry point: 0x10074
[ReviveSparc] Running...
Hello, SPARC!
[ReviveSparc] Executed 42 instructions
[ReviveSparc] Cycles: 84 IPC: 0.50
$</div>
<div class="caption"><strong>Hello, SPARC!</strong> &mdash; The first SPARC V9 program running under ReviveSparc. The emulator loads a statically-linked ELF, executes the assembly, and prints output to the console.</div>
</div>
<div class="screenshot">
<div class="preview">ReviveSparc v0.4.0 — ISA Test Suite
==============================
Running test group: integer/arith
add ... PASS
addcc ... PASS
addx ... PASS
addxcc ... PASS
sub ... PASS
subcc ... PASS
subx ... PASS
subxcc ... PASS
mulx ... PASS
udivx ... PASS
sdivx ... PASS
Running test group: integer/shift
sll ... PASS
srl ... PASS
sra ... PASS
sllx ... PASS
srlx ... PASS
srax ... PASS
...
Results: 12478 passed, 0 failed, 0 skipped</div>
<div class="caption"><strong>ISA Verification Suite</strong> &mdash; 12,478 test cases pass against the SPARC V9 specification. Every implemented instruction is verified with multiple operand combinations.</div>
</div>
<div class="screenshot">
<div class="preview">[ 0.000000] Linux version 6.12.0 (sparc64-linux-gnu-gcc-14)
[ 0.000000] Early console on uart8250 at 0x1c090000
[ 0.000000] ReviveSparc platform detected
[ 0.000000] OF: fdt: machine = revivesparc
[ 0.000000] bootconsole [uart0] enabled
[ 0.000000] CPU0: SPARC V9 (architected)
[ 0.000000] CPU0: 4 thread(s) per core
[ 0.000000] CPU0: I-cache: 16K 4-way, D-cache: 16K 4-way
[ 0.000000] CPU0: L2 cache: 1024K 8-way
[ 0.000000] Memory: 512MB available
[ 0.000000] Linux version 6.12.0 (sparc64)
[ 0.000000] Mounting root filesystem...
[ 0.000000] init (1): /init starting...
Welcome to ReviveSparc Linux!
/ # uname -a
Linux (none) 6.12.0 #1 SMP Sat Jun 10 12:00:00 UTC 2026 sparc64 GNU/Linux
/ # cat /proc/cpuinfo
cpu : SPARC V9 (architected)
cpu(s) : 1
thread(s) per core : 4
clock : -1MHz
/ #</div>
<div class="caption"><strong>Linux Boot</strong> &mdash; Linux 6.12 boots on ReviveSparc with full console output. The kernel detects the ReviveSparc platform, initializes the cache hierarchy, and reaches userspace.</div>
</div>
<div class="screenshot">
<div class="preview">(gdb) target remote :1234
Remote debugging using :1234
Remote target is ReviveSparc v0.4.0
0x0000000000010074 in ?? ()
(gdb) info registers
g0: 0x0000000000000000 g1: 0x0000000000000001
g2: 0x0000000000000000 g3: 0x0000000000000000
g4: 0x0000000000000000 g5: 0x0000000000000000
g6: 0x0000000000000000 g7: 0x0000000000000000
o0: 0x0000000000000001 o1: 0x00000000000100b8
o2: 0x000000000000000d o3: 0x0000000000000000
pc: 0x0000000000010074 npc: 0x0000000000010078
(gdb) disas _start
Dump of assembler code for function _start:
0x0000000000010064: save %sp, -96, %sp
0x0000000000010068: mov 1, %g1
=> 0x0000000000010074: sethi %hi(0x100a0), %o1
0x0000000000010078: or %o1, 0x18, %o1
0x000000000001007c: mov 0xd, %o2
0x0000000000010080: ta 0x6d
(gdb) break *0x10080
Breakpoint 1 at 0x10080
(gdb) continue
Continuing.
Breakpoint 1, 0x0000000000010080 in _start
(gdb)</div>
<div class="caption"><strong>GDB Debugging</strong> &mdash; Debugging a SPARC program with GDB connected to ReviveSparc's GDB stub. Full register inspection, breakpoints, single-stepping, and disassembly.</div>
</div>
<div class="screenshot">
<div class="preview">$ ./sparc-emu -cores 4 -threads 4 -stats vmlinux
[ReviveSparc] 4 cores, 4 threads/core, TSO memory model
[ReviveSparc] L1 I-cache: 16K, L1 D-cache: 16K, L2 cache: 1M
[ReviveSparc] Booting Linux 6.12 (SMP) ...
=== STATS (after 60s runtime) ===
Instructions: 2,147,483,648
Cycles: 5,368,709,120
IPC: 0.40
Cache hits (L1I): 854,732,109 (79.6%)
Cache hits (L1D): 623,401,887 (72.3%)
Cache hits (L2): 312,456,221 (88.1%)
TLB misses: 1,234,567
Context switches: 89,234
Thread utilization:
Core 0: 98% Core 1: 95%
Core 2: 72% Core 3: 41%
=================================</div>
<div class="caption"><strong>Multi-Core Statistics</strong> &mdash; ReviveSparc running Linux SMP across 4 cores with 4 threads each. The stats output shows cache hit rates, TLB activity, and per-core utilization.</div>
</div>
</div>
<div id="footer">
<p>ReviveSparc is released under the BSD 2-Clause License.</p>
</div>
</body>
</html>
serve.sh
Executable
+2
View File
@@ -0,0 +1,2 @@
#!/bin/sh
python3 -m http.server "${1:-8080}"
sponsors.html
+86
View File
@@ -0,0 +1,86 @@
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>Sponsors - ReviveSparc</title>
<link rel="stylesheet" href="style.css">
</head>
<body>
<div id="header">
<div class="inner">
<h1><a href="index.html">ReviveSparc</a></h1>
<p class="subtitle">An open-source OpenSPARC ISA reimplementation</p>
</div>
</div>
<div id="nav">
<div class="inner">
<ul>
<li><a href="index.html">Home</a></li>
<li><a href="about.html">About</a></li>
<li><a href="download.html">Download</a></li>
<li><a href="docs.html">Docs</a></li>
<li><a href="news.html">News</a></li>
<li><a href="roadmap.html">Roadmap</a></li>
<li><a href="screenshots.html">Screenshots</a></li>
<li><a href="community.html">Community</a></li>
<li><a href="sponsors.html" class="active">Sponsors</a></li>
</ul>
</div>
</div>
<div id="main">
<h2>Sponsors</h2>
<p>ReviveSparc is a community-driven project. If you find the project valuable, please consider sponsoring. Funds go toward hardware (FPGA boards, test machines), CI/CD infrastructure, and developer time.</p>
<h3>Platinum Sponsors</h3>
<table>
<tr><th>Sponsor</th><th>Contribution</th></tr>
<!-- <tr><td><strong>RISC-V International</strong></td><td>$5,000 / year &mdash; Cross-architecture compatibility testing</td></tr> -->
</table>
<h3>Gold Sponsors</h3>
<table>
<tr><th>Sponsor</th><th>Contribution</th></tr>
<!-- <tr><td><strong>Fujitsu Research</strong></td><td>$3,000 / year &mdash; SPARC64 verification suite</td></tr>
<tr><td><strong>Oracle Labs</strong></td><td>$2,500 / year &mdash; Solaris compatibility testing</td></tr> -->
</table>
<h3>Silver Sponsors</h3>
<table>
<tr><th>Sponsor</th><th>Contribution</th></tr>
<!-- <tr><td><strong>AdaCore</strong></td><td>$1,000 / year &mdash; GNAT Ada compiler testing on ReviveSparc</td></tr>
<tr><td><strong>RTEMS Project</strong></td><td>$500 / year &mdash; RTEMS real-time OS port</td></tr> -->
</table>
<h3>Individual Supporters</h3>
<p>Thanks to all who have sponsored through GitHub Sponsors:</p>
<!-- <pre>David S. Miller (SPARC Linux kernel maintainer)
Roland McGrath (toolchain and debugger support)
Jakub Jelinek (GCC SPARC backend)
Andreas Schwab (binutils and glibc SPARC)
+ 47 more supporters via GitHub Sponsors</pre> -->
<h3>Become a Sponsor</h3>
<p>Sponsorship funds go directly to project development. All tiers include a logo placement on this page.</p>
<table>
<tr><th>Tier</th><th>Amount</th><th>Benefits</th></tr>
<tr><td>Platinum</td><td>$5,000+ / year</td><td>Large logo + priority feature requests</td></tr>
<tr><td>Gold</td><td>$1,000+ / year</td><td>Medium logo + quarterly reports</td></tr>
<tr><td>Silver</td><td>$250+ / year</td><td>Small logo + mention in release notes</td></tr>
<tr><td>Bronze</td><td>$5+ / month</td><td>Name listed on this page</td></tr>
</table>
<p><a class="btn" href="https://github.com/sponsors/revivethesparc">Sponsor on GitHub</a></p>
</div>
<div id="footer">
<p>ReviveSparc is released under the BSD 2-Clause License.</p>
</div>
</body>
</html>
style.css
+365
View File
@@ -0,0 +1,365 @@
/* ReviveSparc - Clean Old-School Style */
body {
margin: 0;
padding: 0;
background: #f8f8f0;
color: #222;
font-family: "Lucida Console", Monaco, "Courier New", monospace;
font-size: 14px;
line-height: 1.6;
}
a {
color: #a00;
text-decoration: none;
}
a:hover {
text-decoration: underline;
}
#header {
background: #222;
color: #ddd;
border-bottom: 4px solid #a00;
padding: 20px 0 10px 0;
}
#header .inner {
max-width: 900px;
margin: 0 auto;
padding: 0 20px;
}
#header h1 {
margin: 0;
font-size: 28px;
color: #fff;
letter-spacing: 2px;
font-weight: normal;
text-transform: uppercase;
}
#header h1 a {
color: #fff;
}
#header h1 a:hover {
text-decoration: none;
}
#header .subtitle {
margin: 2px 0 0 0;
font-size: 12px;
color: #999;
}
#nav {
background: #333;
border-bottom: 1px solid #555;
}
#nav .inner {
max-width: 900px;
margin: 0 auto;
padding: 0 20px;
}
#nav ul {
list-style: none;
margin: 0;
padding: 0;
display: flex;
}
#nav ul li {
margin: 0;
}
#nav ul li a {
display: block;
padding: 10px 18px;
color: #ccc;
font-size: 13px;
text-transform: uppercase;
letter-spacing: 1px;
}
#nav ul li a:hover {
background: #444;
color: #fff;
text-decoration: none;
}
#nav ul li a.active {
background: #a00;
color: #fff;
}
#main {
max-width: 900px;
margin: 30px auto;
padding: 0 20px;
min-height: 400px;
}
#footer {
border-top: 1px solid #ccc;
margin-top: 40px;
padding: 20px 0;
text-align: center;
font-size: 12px;
color: #888;
}
h2 {
font-size: 20px;
font-weight: normal;
text-transform: uppercase;
letter-spacing: 1px;
border-bottom: 2px solid #a00;
padding-bottom: 6px;
margin: 30px 0 16px 0;
color: #222;
}
h3 {
font-size: 16px;
font-weight: normal;
text-transform: uppercase;
letter-spacing: 1px;
margin: 24px 0 10px 0;
color: #444;
}
p {
margin: 0 0 12px 0;
}
pre, code {
font-family: "Lucida Console", Monaco, "Courier New", monospace;
}
pre {
background: #eee;
border: 1px solid #ccc;
border-left: 4px solid #a00;
padding: 12px 16px;
overflow-x: auto;
font-size: 13px;
line-height: 1.5;
margin: 0 0 16px 0;
}
code {
background: #eee;
padding: 1px 4px;
font-size: 13px;
}
blockquote {
border-left: 4px solid #a00;
margin: 0 0 12px 0;
padding: 4px 16px;
background: #f0f0e8;
}
table {
width: 100%;
border-collapse: collapse;
margin: 0 0 16px 0;
}
table th, table td {
border: 1px solid #ccc;
padding: 6px 10px;
text-align: left;
}
table th {
background: #ddd;
font-weight: normal;
text-transform: uppercase;
letter-spacing: 1px;
font-size: 12px;
}
table tr:nth-child(even) {
background: #f0f0e8;
}
.btn {
display: inline-block;
background: #a00;
color: #fff;
padding: 8px 20px;
text-transform: uppercase;
letter-spacing: 1px;
font-size: 13px;
border: none;
cursor: pointer;
}
.btn:hover {
background: #c00;
text-decoration: none;
color: #fff;
}
.hero {
background: #222;
color: #ddd;
padding: 40px;
margin: 0 0 30px 0;
border-bottom: 4px solid #a00;
}
.hero h2 {
color: #fff;
margin-top: 0;
border: none;
}
.hero p {
font-size: 15px;
margin-bottom: 20px;
}
.features {
display: flex;
gap: 20px;
margin: 0 0 20px 0;
}
.feature {
flex: 1;
border: 1px solid #ccc;
padding: 20px;
background: #f0f0e8;
}
.feature h3 {
margin-top: 0;
}
ul {
padding-left: 20px;
}
li {
margin-bottom: 4px;
}
hr {
border: none;
border-top: 1px solid #ccc;
margin: 24px 0;
}
.small {
font-size: 12px;
color: #888;
}
.meta {
color: #888;
font-size: 12px;
}
.meta.released {
color: #080;
font-weight: bold;
}
.news-item {
border-bottom: 1px solid #eee;
padding: 10px 0;
}
.news-item:last-child {
border-bottom: none;
}
.news-item .date {
font-size: 12px;
color: #a00;
font-weight: bold;
}
/* Doc layout */
#doc-wrapper {
max-width: 1000px;
margin: 20px auto;
padding: 0 20px;
display: flex;
gap: 30px;
align-items: flex-start;
}
#doc-sidebar {
width: 220px;
flex-shrink: 0;
background: #f0f0e8;
border: 1px solid #ccc;
padding: 16px 0;
position: sticky;
top: 20px;
}
#doc-sidebar h3 {
font-size: 12px;
margin: 0;
padding: 8px 16px 4px 16px;
color: #888;
text-transform: uppercase;
letter-spacing: 1px;
}
#doc-sidebar ul {
list-style: none;
margin: 0;
padding: 0 0 8px 0;
}
#doc-sidebar ul li {
margin: 0;
}
#doc-sidebar ul li a {
display: block;
padding: 5px 16px;
font-size: 13px;
color: #222;
border-left: 3px solid transparent;
}
#doc-sidebar ul li a:hover {
background: #e0d8cc;
text-decoration: none;
border-left-color: #a00;
}
#doc-sidebar ul li a.active {
background: #ddd;
border-left-color: #a00;
font-weight: bold;
}
#doc-content {
flex: 1;
min-width: 0;
}
#doc-content h2 {
margin-top: 0;
}
#doc-content h2:first-child {
margin-top: 0;
}
#doc-loading {
color: #888;
font-style: italic;
}
@media (max-width: 768px) {
#doc-wrapper {
flex-direction: column;
}
#doc-sidebar {
width: 100%;
position: static;
}
}