* Initial

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+# Memory Model
+
+ReviveSparc implements the SPARC V9 memory architecture, including the cache hierarchy, MMU, and memory ordering models.
+
+## Cache Hierarchy
+
+```
+CLIENT (Core)
+  |
+  +-- L1 I-Cache (16 KB, 4-way, 32-byte line)
+  +-- L1 D-Cache (16 KB, 4-way, 32-byte line)
+  |
+  +-- L2 Cache (shared, 512 KB - 4 MB, 8-way)
+  |
+  +-- Main Memory (DDR4, configurable)
+```
+
+### L1 Caches
+
+- **Capacity**: 16 KB each for instructions and data
+- **Associativity**: 4-way set associative
+- **Line size**: 32 bytes
+- **Latency**: 2 cycles (hit), 1 cycle (tag check)
+- **Policy**: Write-back (D-cache), read-only (I-cache)
+- **Coherency**: MOESI protocol between cores
+
+### L2 Cache
+
+- **Capacity**: Configurable (512 KB to 4 MB)
+- **Associativity**: 8-way set associative
+- **Line size**: 64 bytes
+- **Latency**: 12 cycles (hit)
+- **Policy**: Write-back, write-allocate
+- **Coherency**: Inclusive of L1 (snoop filter)
+
+## MMU (Memory Management Unit)
+
+The SPARC Reference MMU provides virtual-to-physical address translation.
+
+### Address Spaces
+
+| Mode | Virtual Address Width | Physical Address Width |
+|------|----------------------|----------------------|
+| 32-bit (V8 compat) | 32 bits | 40 bits |
+| 64-bit (V9) | 44 bits | 44 bits |
+
+### TLB Structure
+
+```
+ITLB (64 entries)
+  Fully associative
+  Supports 8 KB, 64 KB, 256 KB, 4 MB pages
+
+DTLB (64 entries)
+  Fully associative
+  Supports same page sizes as ITLB
+```
+
+### Translation Process
+
+```
+Virtual Address (44 bits)
+  |
+  +-- VPN[0:2] --> TLB Lookup (parallel)
+  |                  |
+  |           +-- Hit? --> PPN + Offset --> Physical Address
+  |           +-- Miss --> TLB Miss Trap (TLB miss handler)
+  |
+  +-- Offset --> Direct to physical address
+```
+
+### TSB (Translation Storage Buffer)
+
+The TSB is a software-managed cache of page table entries. On a TLB miss, the trap handler searches the TSB before walking the full page table.
+
+## Memory Ordering
+
+ReviveSparc supports three memory models:
+
+### Total Store Order (TSO)
+
+The default SPARC V9 model:
+
+- Stores appear in program order to all observers
+- Loads may pass stores (store buffer forwarding)
+- Atomic operations provide full ordering
+
+### Partial Store Order (PSO)
+
+Relaxed store ordering:
+
+- Stores to different locations may be reordered
+- Stores to the same location appear in order
+- MEMBAR is required for ordering constraints
+
+### Relaxed Memory Order (RMO)
+
+Maximum relaxation:
+
+- Loads and stores may be reordered freely
+- All ordering is explicit via MEMBAR instructions
+- Highest performance on multi-core configurations
+
+## Atomic Operations
+
+| Instruction | Description |
+|-------------|-------------|
+| `CAS` | Compare and Swap (32-bit) |
+| `CASX` | Compare and Swap (64-bit) |
+| `SWAP` | Atomic swap |
+| `LDSTUB` | Atomic load-and-store-byte |
+| `CASA` | Compare and Swap (alternate space) |
+| `CASXA` | Compare and Swap (alternate space, 64-bit) |
+
+## Configuration
+
+Memory parameters can be configured at startup:
+
+```bash
+./sparc-emu -l1i 16k -l1d 16k -l2 1m -mem tso kernel.bin
+```
+
+Or via the C API:
+
+```c
+sparc_mem_config_t mem = {
+    .l1i_size      = 16 * 1024,
+    .l1d_size      = 16 * 1024,
+    .l2_size       = 1 * 1024 * 1024,
+    .memory_model  = MEM_TSO,
+    .num_cores     = 4
+};
+sparc_t *cpu = sparc_new_with_config(&mem);
+```